- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67327 > 5962-8876404XX (ANALOG DEVICES INC) 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 PDF資料下載
參數(shù)資料
| 型號： | 5962-8876404XX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, GLASS SEALED, CERDIP-28 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 366K |
| 代理商： | 5962-8876404XX |
AD7824/AD7828
REV. D
–9–
MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors which have a WAIT
state facility, whereby a READ instruction cycle can be extended to
accommodate slow memory devices. A READ operation brings
CS and RD low which starts a conversion. The analog multiplexer
address inputs must remain valid while
CS and RD are low.
The data bus (DB7–DB0) remains in the three-state condition
until conversion is complete. There are two converter status
outputs on the AD7824/AD7828, interrupt (
INT) and ready
(RDY) which can be used to drive the microprocessor READY/
WAIT input. The RDY is an open drain output (no internal
pull-up device) which goes low on the falling edge of
CS and
goes high impedance at the end of conversion, when the 8-bit
conversion result appears on the data outputs. If the RDY status
is not required, then the external pull-up resistor can be omitted
and the RDY output tied to GND. The
INT goes low when
conversion is complete and returns high on the rising edge of
CS or RD.
MODE 1
Mode 1 operation is designed for applications where the micro-
processor is not forced into a WAIT state. A READ operation
takes
CS and RD low which triggers a conversion (see Figure
15). The multiplexer address inputs are latched on the rising
edge of
RD. Data from the previous conversion is read from the
three-state data outputs (DB7–DB0). This data may be disre-
garded if not required. Note, the RDY output (open drain out-
put) does not provide any status information in this mode and
must be connected to GND. At the end of conversion
INT
goes low. A second READ operation is required to access the
new conversion result. This READ operation latches a new
address into the multiplexer inputs and starts another conversion.
INT returns high at the end of the second READ operation,
when
CS or RD returns high. A delay of 2.5
s must be allowed
between READ operations.
Figure 14. Mode 0 Timing Diagram
Figure 15. Mode 1 Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-8876701LA | PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP24 |
| 5962-8877601XX | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, DIP24 |
| 5962-89441012A | SPECIALTY ANALOG CIRCUIT, CQCC20 |
| 5962-8944101VCA | SPECIALTY ANALOG CIRCUIT, CDIP14 |
| 5962-8944101CA | SPECIALTY ANALOG CIRCUIT, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-8876501RX | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DUAL 12-BIT IC RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風格: 封裝 / 箱體:TSSOP 封裝:Reel |
| 5962-8876502RA | 制造商:Rochester Electronics LLC 功能描述:12-BIT DAC IC - Bulk |
| 5962-8876502RX | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DUAL 12-BIT IC RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風格: 封裝 / 箱體:TSSOP 封裝:Reel |
| 5962-88766013A | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 28-Pin CLLCC 制造商:Analog Devices 功能描述:DAC 1CH R-2R 12-BIT 28CLLCC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:PARALLEL 12-BIT DACPORT - Bulk 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC PARALLEL 12-BIT DACPORT |
| 5962-8876601LA | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12 BIT V-OUT IC RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風格: 封裝 / 箱體:TSSOP 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。