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參數(shù)資料
| 型號(hào)： | 5962-8876404XX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, GLASS SEALED, CERDIP-28 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 366K |
| 代理商： | 5962-8876404XX |
AD7824/AD7828
REV. D
–10–
MICROPROCESSOR INTERFACING
The AD7824/AD7828 is designed to interface to microproces-
sors as Read Only Memory (ROM). Analog channel selection,
conversion start and data read operations are controlled by
CS,
RD and the channel address inputs. These signals are common
to all memory peripheral devices.
Z80 MICROPROCESSOR
Figure 16 shows a typical AD7824/AD7828–Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow-
ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the con-
version result.
LD B, (C000)
At the beginning of the instruction cycle when the ADC ad-
dress is selected, RDY asserts the WAIT input, so that the Z80
is forced into a WAIT state. At the end of conversion RDY
returns high and the conversion result is placed in the B register
of the microprocessor.
Figure 16. AD7824/AD7828–Z80 lnterface
Table II. Address Channel Selection
AD7824
AD7828
Address
Channel
C000
1
C001
2
C002
3
C003
4
C004
5
C005
6
C006
7
C007
8
MC68000 MICROPROCESSOR
Figure 17 shows a MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
to any of the addresses in Table II starts a conversion and reads
the conversion result.
MOVEB $C000,D0
Once conversion has begun, the MC68000 inserts WAIT states,
until INT goes low asserting DTACK at the end of conversion.
The microprocessor then places the conversion results in the
D0 register.
Figure 17. AD7824/AD7828–MC68000 Interface
TMS32010 MICROCOMPUTER
A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no
P WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
IN, A PA (PA = PORT ADDRESS)
The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5
s must be allowed
between conversions.
Figure 18. AD7824/AD7828–TMS32010 Interface
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