參數(shù)資料
型號(hào)： 5962-8967601XX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
封裝： CERAMIC, LCC-44
文件頁(yè)數(shù)： 22/35頁(yè)
文件大小： 3744K
代理商： 5962-8967601XX
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
29
Maxim Integrated
SPI_DATA_REQUEST Command
The SPI_DATA_REQUEST command (B[23:20] = 1101)
sets up the data request for future SPI_READ_DATA
operations. SPI_READ_DATA is used to fetch the current
settings of the internal CODE, DAC, or RETURN registers
for each channel or the watchdog configuration (WDOG)
settings or the device. The DAC address provided tells
the part which channel location data is to be read back
by the next SPI_READ_DATA command (see Table 3).
Setting the DAC address greater than the number of
available DACS will read back channel 0 content.
The INC bit tells the device how the next readback will
update the DAC address pointer:
0 = Fix the address pointer (all further readbacks con-
tinue at the current address).
1 = Increment the address pointer (further readbacks
continue at the next address, with rollover, default).
The SEL[1:0] bits tells the part what type of data is
requested:
DAC (00): DAC register data (current DAC latch data, not
subject to gating status, default).
CODE (01): CODE register data.
RET (10): RETURN register data.
WDT (11): WDOG register data (DAC selection does not
apply).
Table 10. SPI_DATA_REQUEST Command Format
Table 11. SPI_READ_STATUS Command Format
SPI_READ_STATUS Command
The SPI_READ_STATUS command (B[23:18] = 111000
for DPHA = 0, B[23:18] = 111001 for DPHA = 1) reads
back the watchdog timer and CLR pin status (inten-
tionally repeated to allow maximum interface speeds)
through DOUT.
DIN[18] selects the DOUT Phase (DPHA) to be used
(see the SPI Serial Interface Timing Diagram in Figure 1
for details).
WD_STAT indicates a watchdog timeout condition. It
reads 0 during normal operation, 1 during a timeout.
WD_STAT is not masked by the WD_MASK bit in the
WDOG_CONFIG command.
CLR_STAT indicates the line level of the CLR pin. ‘0’ indi-
cates the CLR input is or was asserted (grounded) during
the current SPI operation. ‘1’ indicates the CLR input is
not currently asserted (VDDIO level).
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1
0
1
DAC SELECTION
INC SEL[1:0]
X
SPI_DATA_REQUEST
DAC Selection
Increment
Data
Selection
00: DAC
01: CODE
10: RET
11: WDT
Don’t Care
Default Value
→
0
1
0
X
Command Byte
Data High Byte
Data Low Byte
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1
0
X
SPI_READ_STATUS (DPHA = 0)
DOUT = WD_STAT (Repeated)
DOUT = CLR_STAT (Repeated)
1
0
1
X
SPI_READ_STATUS (DPHA = 1)
DOUT = WD_STAT (Repeated)
DOUT = CLR_STAT (Repeated)
Command Byte
Data High Byte
Data Low Byte
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