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| 型號： | 5962-8967601XX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 9/35頁 |
| 文件大?。?/td> | 3744K |
| 代理商： | 5962-8967601XX |
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MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
17
Maxim Integrated
Detailed Description
The MAX5723/MAX5724/MAX5725 are 8-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software-selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a fast 4-wire
SPI/QSPI/MICROWIRE/DSP-compatible serial interface
to save board space and reduce the complexity in iso-
lated applications interface. The MAX5723/MAX5724/
MAX5725 include a serial-in/parallel-out shift register,
internal CODE and DAC registers, a power-on-reset
(POR) circuit to initialize the DAC outputs to zero scale
(M/Z = 0) or midscale (M/Z = 1), and control logic.
CLR is available to asynchronously clear the DAC out-
puts to a user-programmable default value, independent
of the serial interface. LDAC is available to simultane-
ously update selected DACs on one or more devices.
The MAX5723/MAX5724/MAX5725 also feature user-
configurable interface watchdog, with status indicated
by the IRQ output.
DAC Outputs (OUT_)
The MAX5723/MAX5724/MAX5725 include internal buf-
fers on all DAC outputs, which provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive resistive loads are as low as 2kI
in parallel with as much as 500pF of capacitance. The
analog supply voltage (VDD) determines the maximum
output voltage range of the devices since it powers the
output buffers. Under no-load conditions, the output buf-
fers drive from GND to VDD, subject to offset and gain
errors. With a 2kω load to GND, the output buffers drive
from GND to within 200mV of VDD. With a 2kω load to
VDD, the output buffers drive from VDD to within 200mV
of GND.
The DAC ideal output voltage is defined by:
OUT
REF
N
D
VV
2
=
×
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
logic input.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents.
Once the device is powered up, each DAC channel can
be independently programmed with a desired RETURN
value using the RETURN command. This becomes the
value the CODE and DAC registers will use in the event
of any watchdog, clear or gate activity, as selected by
the DEFAULT command.
Hardware CLR operations and SW_CLEAR commands
return the contents of all CODE and DAC registers to their
user-selected defaults. SW_RESET commands will reset
CODE and DAC register contents to their M/Z selected
initial codes. A SW_GATE state can be used to momen-
tarily hold selected DAC outputs in their DEFAULT posi-
tions. The contents of CODE and DAC registers can
be manipulated by watchdog timer activity, enabling a
variety of safety features.
Internal Reference
The MAX5723/MAX5724/MAX5725 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF output
for other external circuitry (see the Typical Operating
Circuits) and can drive loads down to 25kI.
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| 5962-8967901XC | 制造商:SEI 功能描述: |
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