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| 型號： | 5962-8967602QX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 17/35頁 |
| 文件大?。?/td> | 3744K |
| 代理商： | 5962-8967602QX |
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MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
24
Maxim Integrated
WDOG Command
The WDOG command (B[23:20] = 0001) updates the
watchdog timeout settings and safety levels for the
device. Timeout thresholds are selected in 1ms incre-
ments (1ms to 4095ms are available). The WD_MASK bit
can be used to mask the IRQ operation in response to the
watchdog status, if WD_MASK = 1, watchdog alarms will
not assert IRQ . The watchdog alarm status (WD bit) can
be polled using the available SPI status readback com-
mands regardless of WD_MASK settings. A write to this
register will not reset a previously triggered watchdog
alarm (use the WD_RESET command for this purpose).
The watchdog timer refresh and timeout behavior is
defined by the programmable safety level below.
Available safety levels (WL[1:0]):
Low (00): Watchdog timer will refresh with the execution
of any valid user mode command or no-op. Any success-
ful slave address acknowledge qualifies to restart the
watchdog timer (run to the ninth SCL edge), regardless
of the command which follows. Issuing hardware CLR or
LDAC falling edge will also refresh the watchdog timer.
A triggered watchdog alarm does not prevent writes to
any register. LDAC and CLR inputs still function after a
watchdog timeout event.
Medium (01): A WD_REFRESH command must be execut-
ed in order to refresh the watchdog timer. Other commands
as well as LDAC or CLR activity do not refresh the watch-
dog timer. A triggered watchdog alarm does not prevent
writes to any register. LDAC and CLR inputs still function
after a watchdog timeout event.
High (10): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands as well
as LDAC or CLR activity do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution
of all POWER, REF, CONFIG, DEFAULT, and RETURN
commands. LDAC and CLR inputs still function after a
watchdog timeout event.
Max (11): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands, as well
as LDAC or CLR activity, do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution of
all POWER, REF, CONFIG, DEFAULT, and RETURN com-
mands. LDAC and CLR are gated and do not function
after a watchdog timeout event.
Table 5. Watchdog Safety Level Protection
*Unless otherwise affected by Watchdog HOLD or CLR configurations as set by the CONFIG command. See the CONFIG register
definition for details.
Table 4. WDOG Command Format
WATCHDOG
SAFETY
LEVEL
ANY COMMAND
REFRESHES
WDT
CLR/LDAC
REFRESHES
WDT
SW_RESET
PLUS WD_RFRS
REFRESHES WDT
ALL REGISTERS
ACCESSIBLE AFTER
WDT TIMEOUT*
CLR/LDAC AFFECT
DAC REGISTERS
AFTER WDT TIMEOUT*
00 (Low)
X
01 (Med)
—
X
10 (High)
—
X
—
X
11 (Max)
—
X
—
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
B8
B7 B6 B5 B4
B3
B2 B1
B0
0
1
X
C11 C10 C9
C8
C7
C6
C5
C4
C3 C2 C1 C0 WDM WL1 WL0 X
WDOG Command
Don’t Care
Timeout Selection
WD_MASK
WDOG
Safety
Level:
00: Low
01:
Med
10:
High
11: Max
Don’t
Care
Default Value
→
0
X
Command Byte
Data High Byte
Data Low Byte
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