參數(shù)資料
型號(hào)： 5962-8967602QX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 19/35頁(yè)
文件大?。?/td> 3744K
代理商： 5962-8967602QX
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
26
Maxim Integrated
POWER Command
The POWER command (B[23:20] = 0100) updates the
power mode settings of the selected DACs. DACs that
are not selected do not update their power settings in
response to the command. The new power setting is
determined by bits PD[1:0] (B[7:6]) while the affected
DAC(s) are selected using B[15:8]). If all DACs are pow-
ered down and the RF2 bit is not set, the device enters
a STANDBY mode (all analog circuitry is disabled). This
command is inaccessible when a watchdog timeout has
occurred and the watchdog timer is configured with a
safety level of high or max.
Available power modes (PD[1:0]):
Normal (00): DAC channel is active (default).
PD 1kω (01): Power down with 1kω termination to GND.
PD 100kω (10): Power down with 100kω termination to
GND.
PD Hi-Z (11): Power down with high-impedance output.
CONFIG Command
The CONFIG command (B[23:16] = 0101) updates the
watchdog, gate, load, and clear mode settings of the
selected DACs. DACs which are not selected do not
update their settings in response to the command. The
new mode settings to be written are determined by bits
B[7:3] while the affected DAC(s) are selected by B[15:8].
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
Watchdog Configuration:
WDOG Config settings are written by WC[1:0] (B[7:6]):
DISABLE (WC = 00): Watchdog timeout does not affect
the operation of the selected DAC.
GATE (WC = 01): DAC code is gated to DEFAULT value
in response to watchdog timeouts. Unless otherwise
prohibited by the watchdog safety level, LDAC, CLR,
and write operations to the CODE and DAC registers are
accepted but will not be reflected on the DAC output until
the watchdog timeout status is reset.
CLR (WC = 10): CODE and DAC register contents are
cleared to DEFAULT value in response to watchdog time-
outs. All writes to CODE and DAC registers are ignored
and LDAC or CLR input activity has no effect until the
watchdog timeout status is reset, regardless of watchdog
safety level.
HOLD (WC = 11): DAC code is held at its previously
programmed value in response to watchdog timeout.
All writes to DAC and CODE registers are ignored and
LDAC or CLR input activity has no effect until the watch-
dog timeout status is reset, regardless of watchdog
safety level.
Note: For the watchdog to timeout and have an impact,
the function must first be enabled and configured using
the WDOG command.
Table 7. POWER Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7
B6 B5 B4 B3 B2 B1 B0
0
1
0
7
6
5
4
3
2
1
0
PD1 PD0 X
X
POWER Command
Reserved
Multiple DAC Selection
Power
Mode:
00 =
Normal
01 = 1k
W
10 =
100k
W
11 = Hi-Z
Don’t Care
Default Value
→
1
0
X
Command Byte
Data High Byte
Data Low Byte
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