參數(shù)資料
型號(hào)： 5962-8967602XX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
封裝： CERAMIC, LCC-44
文件頁(yè)數(shù)： 10/35頁(yè)
文件大?。?/td> 3744K
代理商： 5962-8967602XX
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
18
Maxim Integrated
External Reference
The external reference input has a typical input impedance
of 100kI and accepts an input voltage from +1.24V to VDD.
Apply an external voltage between REF and GND to use
an external reference. The MAX5723/MAX5724/MAX5725
power up and reset to external reference mode. Visit
list of available external voltage-reference devices.
M/Z Input
The MAX5723/MAX5724/MAX5725 feature a pin-select-
able DAC reset state using the M/Z input. Upon a power-
on reset, all CODE and DAC data registers are reset to
zero scale (M/Z = GND) or midscale (M/Z = VDD). M/Z is
referenced to VDD (not VDDIO). In addition, M/Z must be
valid at the time the device is powered up—connect M/Z
directly to VDD or GND.
Load DAC (LDAC) Input
The MAX5723/MAX5724/MAX5725 feature an active-low
asynchronous LDAC logic input that allows DAC outputs
to update simultaneously. Connect LDAC to VDDIO or
keep LDAC high during normal operation when the
device is controlled only through the serial interface.
Drive LDAC low to update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updat-
ing the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
Clear (CLR) Input
The MAX5723/MAX5724/MAX5725 feature an asynchro-
nous active-low CLR logic input that simultaneously
sets all selected DAC outputs to their programmable
DEFAULT states. Driving CLR low clears the contents of
both the CODE and DAC registers and also ignores any
on-going SPI command which modifies registers associ-
ated with a DAC configured to accept clear operations.
To allow a new SPI command, drive CLR high, satisfying
the tCSC timing requirement. A software CONFIG com-
mand can be used to configure the clear operation of
each DAC independently.
Watchdog Feature
The MAX5723/MAX5724/MAX5725 feature an interface
watchdog timer with programmable timeout duration. This
monitors the I/O interface for activity and integrity. If the
watchdog is enabled, the host processor must write a valid
command to the device within the timeout period to prevent
a timeout. If the watchdog is allowed to timeout, selected
DAC outputs are returned to the programmable DEFAULT
state, protecting the system against control faults.
By default, all watchdog features are disabled; users
wishing to activate any watchdog feature must configure
the device accordingly. Individual DAC channels can
be configured using the CONFIG command to accept
the watchdog alarm and to gate, clear, or hold their out-
puts in response to an alarm. A watchdog refresh event
and watchdog behavior upon timeout is defined by a
programmable safety level using the WDOG_CONFIG
command.
IRQ Output
The MAX5723/MAX5724/MAX5725 feature an active-low
open-drain interrupt output indicating to the host when a
watchdog timeout has occurred.
Interface Power Supply (VDDIO)
The MAX5723/MAX5724/MAX5725 feature a separate
supply input (VDDIO) for the digital interface (1.8V to
5.5V). Connect VDDIO to the I/O supply of the host pro-
cessor.
SPI Serial Interface
The MAX5723/MAX5724/MAX5725 4-wire serial inter-
face is compatible with MICROWIRE, SPI, QSPI, and
DSPs. The interface provides three inputs, SCLK, CSB,
and DIN. The chip-select input (CSB, active-low) frames
the data loaded through the serial data input (DIN).
Following a CSB input high-to-low transition, the data
is shifted in synchronously and latched into the input
register on each falling edge of the serial clock input
(SCLK). Each serial operation word is 24-bits long. The
DAC data is left justified as shown in Table 1. The serial
Table 1. Format DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5723
D7
D6
D5
D4
D3
D2
D1
D0
X
MAX5724
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
MAX5725
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
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5962-8967601XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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