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參數(shù)資料
| 型號(hào)： | 5962-8967602XX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 3744K |
| 代理商： | 5962-8967602XX |
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MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
19
Maxim Integrated
input register transfers its contents to the destination
registers after loading 24 bits of data on the 24th SCLK
falling edge. To initiate a new SPI operation, drive CSB
high and then low to begin the next operation sequence,
being sure to meet all relevant timing requirements.
During CSB high periods, SCLK is ignored, allowing
communication to other devices on the same bus. SPI
operations consisting of more than 24 SCLK cycles are
executed on the 24th SCLK falling edge, using the first
three bytes of data available. SPI operations consisting
of less than 24 SCLK cycles will not be executed. The
content of the SPI operation consists of a command
byte followed by a two-byte data word.
The DOUT phase for all SPI_READ commands is deter-
mined by the readback command used, allowing the
selection of the SCLK DOUT update edge best suited to
the digital I/O implementation, maximizing data transfer
speed and/or timing margin.
Guaranteed non-zero DOUT hold times allow the micro-
processor to strobe DOUT on the same edge as the
MAX5723/MAX5724/MAX5725 updates for fastest SPI
read mode transfers. For example, if DPHA = 0 is used,
the MAX5723/MAX5724/MAX5725 update DOUT in
response to SCLK falling edges 8-23, while a micropro-
cessor (P) with low data hold time requirements can
strobe in the DOUT data on SCLK falling edges 9-24.
The device supports readback speeds of up to 25MHz
for a microprocessor with 5ns data input setup require-
ments and allowing 35ns for tDOT at VDDIO > 2.7V.
Variable DOUT phase also supports microprocessors
with longer data input hold time requirements. For
example, if DPHA = 1 is used, the MAX5723/MAX5724/
MAX5725 updates DOUT in response to SCLK rising
edges 9-24 while the microprocessor can strobe in the
DOUT data on SCLK falling edges 9-24. The device
supports readback speeds up to 12.5MHz for a P with
5ns data input setup requirements and allowing 35ns for
tDOT (assuming 50% duty cycle SCLK).
For improved readback speed while monitoring device
status, the SPI_READ_STATUS command repeats the
device status information for multiple bits, allowing
polling of the device at maximum interface speeds (up
to 50MHz when the readback strobe is placed away
from DOUT transition edges). This transfer speed can-
not be achieved for other forms of readback using the
SPI_READ_DATA command, where more DOUT bus
transitions occur.
Figure 1 shows the timing diagram for the complete
4-wire serial interface transmission. The DAC code
settings (D) for the MAX5723/MAX5724/MAX5725 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
typical SPI circuit application.
SPI User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5723/MAX5724/MAX5725.
Table 2 provides detailed information about the Command
Registers.
Figure 2. Typical SPI Application Circuit
MAX5723
MAX5724
MAX5725
CSB
SCLK
DIN
DOUT
CSB
SCLK
DIN
DOUT
CSB
CSB3
CSB2
SCLK
DIN
CSB1
RPU = 5kI
+5V
SCLK
MOSI
MISO
IRQ
C
IRQ
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