參數(shù)資料
型號(hào): 5962-8967602XX
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
封裝: CERAMIC, LCC-44
文件頁(yè)數(shù): 20/35頁(yè)
文件大?。?/td> 3744K
代理商: 5962-8967602XX
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
27
Maxim Integrated
Table 8. CONFIG Command Format
Gate Configuration:
The DAC GATE setting is written by GTB (B5); GATE
operation is as follows:
GTB = 0: Enables software gating function (default), DAC
outputs are gated to their DEFAULT settings as long as
the device remains in GATE mode (set by SW_GATE_
SET and removed by SW_GATE_CLR).
GTB = 1: Disable software gating function, DAC outputs
are not impacted by GATE mode.
Load Configuration:
The LDAC_ENB setting is written by LDB (B4);
LDAC_ENB operation is as follows:
LDB = 0: DAC latch is operational, enabling LDAC and
LOAD functions (default).
LDB = 1: DAC latch is transparent, the CODE register
content controls the DAC output directly.
Clear Configuration:
CLEAR_ENB setting is written by CLB (B3); CLEAR_ENB
operation is as follows:
CLB = 0: Clear input and command functions impact the
DAC (default), clearing CODE and DAC registers to their
DEFAULT value.
CLB = 1: Clear input and command functions have no
effect on the DAC.
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2 B1 B0
0
1
0
1
0
7
6
5
4
3
2
1
0 WC1 WC0 GTB LDB CLB
X
CONFIG Command
Reserved
Multiple DAC Selection
WDOG
Config:
00:
DISABLE
01: GATE
10: CLR
11: HOLD
GATE_ENB
LDAC_ENB
CLEAR_ENB
Don’t Care
Default Value
1
0
X
Command Byte
Data High Byte
Data Low Byte
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5962-8967601XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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