參數(shù)資料
型號(hào)： 5962-8967901QX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 11/30頁(yè)
文件大小： 4271K
代理商： 5962-8967901QX
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
19
Maxim Integrated
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in Table 3.
Interface Verification I2C
Readback Operations
While the MAX5813/MAX5814/MAX5815 support stan-
dard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5813/
MAX5814/MAX5815. The master still has control of the
SCL line but the MAX5813/MAX5814/MAX5815 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5813/MAX5814/
MAX5815 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involv-
ing other devices do not impact the MAX5813/MAX5814/
MAX5815 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
Table 3. Standard I2C User Readback Data
Table 4. Format DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5813
D7
D6
D5
D4
D3
D2
D1
D0
x
MAX5814
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
MAX5815
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
READBACK DATA LOW BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7
B6
B5 B4
B3
B2
B1
B0
0
DAC selection
CODEn[11:4]
CODEn[3:0]
0
1
DAC selection
DACn[11:4]
DACn[3:0]
0
1
0
DAC selection
DACn[11:4]
DACn[3:0]
0
1
DAC selection
DACn[11:4]
DACn[3:0]
0
1
0
X
0
0 PWD PWC PWB PWA
1
0
CODEA[11:4]
CODEA[3:0]
0
1
0
1
DACA[11:4]
DACA[3:0]
0
1
0
1
0
1
0
DACA[11:4]
DACA[3:0]
0
1
0
1
0
1
DACA[11:4]
DACA[3:0]
0
Any other command (TSSOP)
1111 1000
000
REV_ID[2:0]
(010)
REF MODE
RF[1:0]
Any other command (WLP)
1001 1000
000
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