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參數(shù)資料
| 型號： | 5962-9688601QRX |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 2/36頁 |
| 文件大?。?/td> | 875K |
| 代理商： | 5962-9688601QRX |
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TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
Hi-Z
(see Note A)
B3
B2
B1
B0
t(conv)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
Access Cycle B
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
12
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
(see Note A)
B3
B2
B1
B0
t(conv)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
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