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參數(shù)資料
| 型號： | 5CGXFC7D7F27C8NES |
| 廠商： | Altera |
| 文件頁數(shù)： | 786/1077頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE V FPGA 150K 672-FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Cyclone® V GX |
| LAB/CLB數(shù)： | 56415 |
| 邏輯元件/單元數(shù)： | 149500 |
| RAM 位總計： | 6656000 |
| 輸入/輸出數(shù)： | 336 |
| 電源電壓： | 1.07 V ~ 1.13 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 672-BGA |
| 供應(yīng)商設(shè)備封裝： | 672-FBGA（27x27） |
| 其它名稱： | 544-2739 |
Table 11-31: Card Read Threshold Guidelines
Card Read Threshold Required?
Is Stopping of Card
Clock Allowed?
Round Trip Delay (Delay_R)
(34)
Bus Speed Modes
Yes
No
Yes
Delay_R > 0.5 * (sdmmc_clk/4)
Delay_R < 0.5 * (sdmmc_clk/4)
SDR25
Yes
No
Yes
Delay_R > 0.5 * (sdmmc_clk/4)
Delay_R < 0.5 * (sdmmc_clk/4)
SDR12
Related Information
Recommended Usage Guidelines for Card Read Threshold
1. The cardthrctl register must be set before setting the cmd register for a data read command.
2. The cardthrctl register must not be set while a data transfer command is in progress.
3. The cardrdthreshold field of the cardthrctl register must be set to at the least the block size
of a single or multiblock transfer. A cardrdthreshold field setting greater than or equal to the block
size of the read transfer ensures that the card clock does not stop in the middle of a block of data.
4. If the round trip delay is greater than half of the card clock period, card read threshold must be enabled
and the card threshold must be set as per guideline 3 to guarantee that the card clock does not stop in
the middle of a block of data.
5. If the cardrdthreshold field is set to less than the block size of the transfer, the host must ensure
that the receive FIFO buffer never overflows during the read transfer. Overflow can cause the card clock
from the controller to stop. The controller is not able to guarantee that the card clock does not stop during
a read transfer.
If the cardrdthreshold field of the cardthrctl register, and the rx_wmark and
dw_dma_multiple_transaction_size
fields of the fifoth register are set incorrectly,
the card clock might stop indefinitely, with no interrupts generated by the controller.
Note:
Card Read Threshold Programming Sequence
Most cards, such as SDHC or SDXC, support block sizes that are either specified in the card or are fixed to
512 bytes. For SDIO, MMC, and standard capacity SD cards that support partial block read
(READ_BL_PARTIAL set to 1 in the CSD register of the card device), the block size is variable and can be
chosen by the application.
(34) Delay_R = Delay_O + tODLY + Delay_I
Where:
Delay_O = sdmmc_clk to sdmmc_cclk_out delay (including I/O pin delay)
Delay_I = Input I/O pin delay + routing delay to the input register
tODLY = sdmmc_cclk_out to card output delay (varies across card manufactures and speed modes)
For the delay numbers needed for above calculation, refer to Arria 10 Datasheet.
SD/MMC Controller
Altera Corporation
cv_54011
Recommended Usage Guidelines for Card Read Threshold
11-58
2013.12.30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5CGXFC7D7F31C8N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone V GX 5648 LABs 480 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| 5CGXFC7D7F31C8NES | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone V GX 5648 LABs 480 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| 5CGXFC9A6U19A7N | 功能描述:IC FPGA 240 I/O 484UBGA 制造商:altera 系列:Cyclone? V GX 零件狀態(tài):有效 LAB/CLB 數(shù):113560 邏輯元件/單元數(shù):301000 總 RAM 位數(shù):14251008 I/O 數(shù):240 柵極數(shù):- 電壓 - 電源:1.07 V ~ 1.13 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C （TJ） 封裝/外殼:484-FBGA 供應(yīng)商器件封裝:484-UBGA（19x19） 標(biāo)準(zhǔn)包裝:84 |
| 5CGXFC9A6U19C7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone V GX 113560 LABs 560 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| 5CGXFC9A6U19I7 | 功能描述:IC FPGA 240 I/O 484UBGA 制造商:altera 系列:Cyclone? V GX 零件狀態(tài):有效 LAB/CLB 數(shù):113560 邏輯元件/單元數(shù):301000 總 RAM 位數(shù):14251008 I/O 數(shù):240 柵極數(shù):- 電壓 - 電源:1.07 V ~ 1.13 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C（TJ） 封裝/外殼:484-FBGA 供應(yīng)商器件封裝:484-UBGA（19x19） 標(biāo)準(zhǔn)包裝:84 |
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