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參數(shù)資料
| 型號： | 5P49EE801NDGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR 28QFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | VersaClock™ |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL，晶體 |
| 輸出： | LVCMOS，LVDS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 150MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 800-2524 |
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IDT5P49EE801
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
4
IDT5P49EE801
REV M 072512
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Differential LVDS interface
levels can be generated for OUT4A/OUT4B when connected to VDDO1=3.3V and registers configured
appropriately. Alway completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All
other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
OUT2
13
O
Adjustable
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
SEL1*
14
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
OUT1
15
O
Adjustable
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDD
16
Power
Device power supply. Connect to 1.8V.
VDD
17
Power
Device power supply. Connect to 1.8V.
OUT0
18
O
Adjustable
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDDO3
19
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels forOUT0-OUT5.
SCLK
20
I
LVTTL
I2C clock. Logic levels set by VDDO1. 5V tolerant.
OUT6B
21
O
Adjustable
Configurable clock output 6B. Single-ended or differential when
combined with OUT6A. Output voltage levels are controlled by
VDDO1.
OUT6A
22
O
Adjustable
Configurable clock output 6A. Single-ended or differential when
combined with OUT6B. Output voltage levels are controlled by
VDDO1.
SDA
23
I/O
Open Drain
Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
VDD
24
Power
Device power supply. Connect to 1.8V.
VDD
25
Power
Device power supply. Connect to 1.8V.
GND
26
Power
Connect to Ground.
XIN/ REF
27
I
LVTTL
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum reference clock input voltage is
1.8V.
XOUT
28
O
LVTTL
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
Pin Name
Pin #
I/O
Pin Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5P49EE801NDGI8 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VERSACLOCK LOW POWER PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 5P49EE802-007NDGI | 制造商:Integrated Device Technology Inc 功能描述: |
| 5P49EE802NDGI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VERSACLOCK LOW POWER PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 5P49EE802NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (4X4MM) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:VERSACLOCK LOW POWER PLL |
| 5P49EE805NDGI | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN Tube 制造商:Integrated Device Technology Inc 功能描述:28 QFN (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL LOW POWER |
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