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參數(shù)資料
| 型號： | 62WV5128ALL |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 中文描述： | 為512k × 8低電壓，超低功耗的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 62WV5128ALL |
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/30/03
1
IS62WV5128ALL
IS62WV5128BLL
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
High-speed access time: 55ns, 70ns
CMOS low power operation
36 mW (typical) operating
9 μW (typical) CMOS standby
TTL compatible interface levels
Single power supply
1.65V – 2.2V V
DD
(IS62WV5128ALL)
2.5V – 3.6V V
DD
(IS62WV5128BLL)
Fully static operation: no clock or refresh
required
Three state outputs
Industrial temperature available
DESCRIPTION
The
ISSI
IS62WV5128ALL / IS62WV5128BLL are high-
speed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin
sTSOP (TYPE I), and 32-pin TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
APRIL 2003
A0-A18
CS1
OE
WE
512K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
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