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參數(shù)資料
| 型號(hào)： | 62WV5128ALL |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 中文描述： | 為512k × 8低電壓，超低功耗的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 83K |
| 代理商： | 62WV5128ALL |
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8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/30/03
IS62WV5128ALL, IS62WV5128BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns
70 ns
Symbol
t
WC
t
SCS1
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Parameter
Write Cycle Time
CS1
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
Min.
55
45
45
0
0
40
25
0
—
5
Max.
—
—
—
—
—
—
—
—
20
—
Min.
70
60
60
0
0
50
30
0
—
5
Max.
—
—
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
V
DD
-0.2V/V
DD
-0.3V and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of
CS1
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
CS1
Controlled,
OE
= HIGH or LOW
)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
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