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參數(shù)資料
| 型號： | 6SP220M |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | DB-LM3S101 Daughterboard |
| 中文描述： | 同步降壓控制器，帶有預(yù)偏置啟動和可選時(shí)鐘同步 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | 6SP220M |
Application Information
(Continued)
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to see.
Software tools such as Excel, MathCAD, and Matlab are
useful for showing how changes in compensation or the
power stage affect system gain and phase.
The power stage modulator provides a DC gain A
that is
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0V
for the LM2747.
The inductor and output capacitor create a double pole at
frequency f
DP
, and the capacitor ESR and capacitance cre-
ate a single zero at frequency f
ESR
. For this example, with
V
IN
= 3.3V, these quantities are:
In the equation for f
, the variable R
is the power stage
resistance, and represents the inductor DCR plus the on
resistance of the top power MOSFET. R
O
is the output
voltage divided by output current. The power stage transfer
function G
PS
is given by the following equation, and
Figure
14
shows Bode plots of the phase and gain in this example.
a = LC
O
(R
O
+ R
C
)
b = L + C
O
(R
O
R
L
+ R
O
R
C
+ R
C
R
L
)
c = R
O
+ R
L
The double pole at 4.5 kHz causes the phase to drop to
approximately -130 at around 10 kHz. The ESR zero, at
20.3 kHz, provides a +90 boost that prevents the phase
from dropping to -180
o
. If this loop were left uncompensated,
the bandwidth would be approximately 10 kHz and the
phase margin 53. In theory, the loop would be stable, but
would suffer from poor DC regulation (due to the low DC
gain) and would be slow to respond to load transients (due to
the low bandwidth.) In practice, the loop could easily become
unstable due to tolerances in the output inductor, capacitor,
or changes in output current, or input voltage. Therefore, the
loop is compensated using the error amplifier and a few
passive components.
For this example, a Type III, or three-pole-two-zero approach
gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including
Type III, a single pole is placed at the origin to boost DC gain
20150964
FIGURE 13. Power Stage and Error Amp
20150969
20150970
FIGURE 14. Power Stage Gain and Phase
L
www.national.com
16
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