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| 型號： | 6SP220M |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | DB-LM3S101 Daughterboard |
| 中文描述： | 同步降壓控制器，帶有預(yù)偏置啟動和可選時鐘同步 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | 6SP220M |
Block Diagram
20150903
Application Information
The LM2747 is a voltage-mode, high-speed synchronous
buck regulator with a PWM control scheme. It is designed for
use in set-top boxes, thin clients, DSL/Cable modems, and
other applications that require high efficiency buck convert-
ers. It has output shutdown (SD), input undervoltage lock-out
(UVLO) mode and power good (PWGD) flag (based on
overvoltage and undervoltage detection). The overvoltage
and undervoltage signals are OR-gated to drive the power
good signal and provide a logic signal to the system if the
output voltage goes out of regulation. Current limit is
achieved by sensing the voltage V
DS
across the low side
MOSFET. The LM2747 is also able to start-up with the
output pre-biased with a load and allows for the switching
frequency to be synchronized with an external clock source.
START UP/SOFT-START
When V
exceeds 2.79V and the shutdown pin (SD) sees
a logic high, the soft-start period begins. Then an internal,
fixed 10 μA source begins charging the soft-start capacitor.
During soft-start the voltage on the soft-start capacitor C
is
connected internally to the non-inverting input of the error
amplifier. The soft-start period lasts until the voltage on the
soft-start capacitor exceeds the LM2747 reference voltage
of 0.6V. At this point the reference voltage takes over at the
non-inverting error amplifier input. The capacitance of C
determines the length of the soft-start period, and can be
approximated by:
Where C
SS
is in μF and t
SS
is in ms.
During soft start the Power Good flag is forced low and it is
released when the FB pin voltage reaches 70% of 0.6V. At
this point the chip enters normal operation mode, and the
output overvoltage and undervoltage monitoring starts.
SETTING THE OUTPUT VOLTAGE
The LM2747 regulates the output voltage by controlling the
duty cycle of the high side and low side MOSFETs (see
Typical Application Circuit).The equation governing output
voltage is:
SETTING THE SWITCHING FREQUENCY
During fixed-frequency mode of operation the PWM fre-
quency is adjustable between 50 kHz and 1 MHz and is set
by an external resistor, R
FADJ
, between the FREQ/SYNC pin
and ground. The resistance needed for a desired frequency
L
www.national.com
8
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