
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
6
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
Tables
Table 11: PSW Bit Functions (SFR 0xD0) ..................................................................................................... 23
Table 17: The S0CON (UART0) Register (SFR 0x98)................................................................................. 27
Table 18: The S1CON (UART1) register (SFR 0x9B).................................................................................. 27
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................ 28
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 29
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 30
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 31
Table 28: The T2CON Bit Functions (SFR 0xC8)........................................................................................ 31
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 31
Table 45: DIO_DIR Control Bit .................................................................................................................... 44
Table 47: EECTRL Bits for 2-pin Interface................................................................................................... 47
Table 48: EECTRL Bits for the 3-Wire Interface .......................................................................................... 48
Table 51: TMUX[4:0] Selections ................................................................................................................. 53