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| 型號： | 71M6532F-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數(shù)： | 96/120頁 |
| 文件大?。?/td> | 2477K |
| 代理商： | 71M6532F-IGTR/F |
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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
77
4.2
I/O RAM Description – Alphabetical Order
The following conventions apply to the descriptions in this table:
Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to
the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining
bits are mapped to 2xxx.
Bits with a R (read) direction can be read by the MPU.
Columns labeled Reset and Wake describe the bit values upon reset and wake, respectively. “NV” in the Wake column means the bit is powered
by the nonvolatile supply and is not initialized. LCD-related registers labeled “L” retain data upon transition from LCD mode to BROWNOUT
mode and vice versa, but do not retain data in SLEEP mode. “–“ means that the value is undefined.
Write-only bits will return zero when they are read.
Table 55: I/O RAM Description - Alphabetical
Name
Location
Reset
Wake
Dir
Description
ADC_E
2005[3]
0
R/W
Enables ADC and VREF. When disabled, removes bias current.
BME
2020[6]
0
–
R/W
Battery Measure Enable. When set, a load current is immediately applied to the battery
and it is connected to the ADC to be measured on Alternative Mux Cycles. See the
MUX_ALT bit.
BOOT_SIZE[7:0]
20A7[7:0]
01
R/W
End of space reserved for boot program. The ending address of the boot region is
1024*BOOT_SIZE.
CE10MHZ
2000[3]
0
R/W
CE clock select. When set, the CE is clocked at 10 MHz. Otherwise, the CE clock
frequency is 5 MHz.
CE_E
2000[4]
0
R/W
CE enable.
CE_LCTN[7:0]
20A8[4:0]
31
R/W
CE program location. The starting address for the CE program is 1024*CE_LCTN.
CHOP_E[1:0]
2002[5:4]
0
R/W
Chop enable for the reference bandgap circuit. The value of CHOP will change on the
rising edge of MUXSYNC according to the value in CHOP_E[1:0]:
00 = toggle, except at the mux sync edge at the end of SUMCYCLE, an alternative
MUX frame is automatically inserted at the end of each accumulation interval.
01 = positive.
10 = reversed.
11 = toggle, no alternative MUX frame is inserted
CHOP_IA
20AC[0]
0
R/W
This bit enables chop mode for the IA current channel (71M6532D/F only). CHOP_I_E
must be set also.
CHOP_IB
20AC[4]
0
R/W
This bit enables chop mode for the IB current channel (71M6532D/F only). CHOP_I_E
must be set also.
CHOP_I_E
20AB[0]
0
R/W
This bit must be set to enable chop mode for the current channels (71M6532D/F only).
CKOUT_E
2004[4]
0
R/W
Control bit for the SEG19/CKOUT pin:
0: The pin is the SEG19 LCD driver
1: The pin is the CK_FIR output (5 MHz in mission mode, 32 kHz in brownout mode)
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