參數(shù)資料
型號: 71V016SA
廠商: Integrated Device Technology, Inc.
英文描述: Power Resistor; Series:MP800; Resistance:1kohm; Resistance Tolerance:+/- 1 %; Power Rating:20W; Temperature Coefficient:-20 to +50 ppm/ C; Terminal Type:Radial Leaded; Package/Case:2-TO-220; Voltage Rating:300V
中文描述: 3.3V的CMOS靜態(tài)RAM 1梅格(64K的x 16位)
文件頁數(shù): 1/9頁
文件大?。?/td> 100K
代理商: 71V016SA
JUNE 2002
DSC-3834/06
1
2000 Integrated Device Technology, Inc.
Features
N
64K x 16 advanced high-speed CMOS Static RAM
N
Equal access and cycle times
— Commercial: 10/12/15/20ns
— Industrial: 12/15/20ns
N
One Chip Select plus one Output Enable pin
N
Bidirectional data inputs and outputs directly
LVTTL-compatible
N
Low power consumption via chip deselect
N
Upper and Lower Byte Enable Pins
N
Single 3.3V power supply
N
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAMorganized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and operation
is froma single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mmFBGA.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A
0
– A
15
Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
8
8
8
I/O
8
I/O
15
I/O
7
I/O
0
3834 drw 01
High
Byte
I/O
Buffer
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
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