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參數(shù)資料
| 型號： | 71V25781YSA166BGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 627K |
| 代理商： | 71V25781YSA166BGI |
6.42
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
11
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
1
0
1
Second Address
0
1
0
1
0
Third Address
1
0
1
0
1
Fourth Address(1)
111
00
1
0
5297 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table(1, 2)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2.
BW3 and BW4 are not applicable for the IDT71V2578.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
XXX
X
Read
H
L
HH
Write all Bytes
L
XXXX
X
Write all Bytes
H
LL
LLL
Write Byte 1(3)
HL
L
HH
H
Write Byte 2(3)
HL
H
L
H
Write Byte 3(3)
HL
H
L
H
Write Byte 4(3)
HL
H
HHL
5297 tbl 12
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
1
0
1
Second Address
0
1
0
1
0
Third Address
1
0
1
0
1
Fourth Address(1)
11
000
11
0
5297 tbl 15
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
5297 tbl 13
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