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參數(shù)資料
| 型號(hào)： | 71V25781YSA166BGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁(yè)數(shù)： | 7/22頁(yè) |
| 文件大?。?/td> | 627K |
| 代理商： | 71V25781YSA166BGI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
6.42
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
15
NOTES:
1.
ZZ
input
is
LOW,
BWE
is
HIGH
and
LBO
is
Don't
Care
for
this
cycle.
2.
O4
(Aw)
represents
the
final
output
data
in
the
burst
sequence
of
the
base
address
Aw.
I1
(Ax)
represents
the
first
input
fr
om
the
external
address
Ax.
I1
(Ay)
represents
the
first
input
from
the
external
address
Ay;
I2
(Ay)
represents
the
next
input
data
in
the
burst
sequence
of
the
base
address
Ay,
etc.
where
A0
and
A1
are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
In
the
case
of
input
I2
(Ay)
this
data
is
valid
for
two
cycles
because
ADV
is
high
and
has
suspended
the
burst.
3.
C
S
0timing
transitions
are
identical
but
inverted
to
the
CE
and
CS
1
signals.
For
example,
when
CE
and
CS
1are
LOW
on
this
waveform,
CS
0is
HIGH.
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
A
D
R
E
S
C
L
K
A
D
S
P
A
D
S
C
tC
Y
C
tS
S
tH
S
tC
H
tC
L
tH
A
tS
A
x
A
y
A
z
A
D
V
D
A
T
A
O
U
T
O
E
tH
C
tS
D
I1
(A
x
)
I1
(A
z
)
I2
(A
y
)
tH
D
tO
H
Z
D
A
T
A
IN
tH
A
V
O
3
(A
w
)
O
4
(A
w
)
C
E
,
C
S
1
tH
W
G
W
tS
W
(N
o
te
3
)
I2
(A
z
)
B
u
rs
t
W
ri
te
B
u
rs
t
R
e
a
d
B
u
rs
t
W
ri
te
S
in
g
le
W
ri
te
I3
(A
z
)
I4
(A
y
)
I3
(A
y
)
I2
(A
y
)
tS
A
V
(A
D
V
H
IG
H
s
u
s
p
e
n
d
s
b
u
rs
t)
I1
(A
y
)
G
W
is
ig
n
o
re
d
w
h
e
n
A
D
S
P
in
it
ia
te
s
a
c
y
cl
e
a
n
d
is
sa
m
p
le
d
o
n
th
e
n
e
x
t
c
lo
ck
ri
s
in
g
e
d
g
e
tS
C
5
2
9
7
d
rw
1
0
.
,
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