參數(shù)資料
型號: 73K224L-IH
廠商: TDK Corporation
英文描述: V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
中文描述: V.22bis/V.22/V.21 /貝爾212A/Bell 103單芯片調(diào)制解調(diào)器
文件頁數(shù): 23/32頁
文件大?。?/td> 206K
代理商: 73K224L-IH
73K224L
V.22bis/V.22/V.21/Bell 212A/Bell 103
Single-Chip Modem
23
DYNAMIC CHARACTERISTICS AND TIMING
(continued)
Timing
(Refer to Timing Diagrams)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Parallel Mode
TAL
CS
/Addr. setup before ALE Low
30
ns
TLA
TLC
CS
/Addr. hold after ALE Low
6
ns
ns
ALE Low to
RD
/
WR
Low
RD
/
WR
Control to ALE High
40
TCL
10
ns
TRD
Data out from
RD
Low
90
ns
TLL
ALE width
25
ns
TRDF
TRW
Data float after
RD
High
40
ns
ns
RD
width
WR
width
70
TWW
70
ns
TDW
Data setup before
WR
High
70
ns
TWD
Data hold after
WR
High
20
ns
Serial Mode
TRCK
Clock High after
RD
Low
Address setup before
RD
Low
250
T1
ns
TAR
0
ns
TRA
Address hold after
RD
Low
350
ns
TRD
RD
to Data valid
300
ns
TRDF
Data float after
RD
High
40
ns
TCKDR
Read Data out after Falling Edge of
EXCLK
300
ns
TWW
TAW
WR
width
350
50
ns
ns
Address setup before
WR
Low
TWA
Address hold after Rising Edge of
WR
50
ns
TCKDW
Write Data hold after Falling Edge
of EXCLK
200
ns
TCKW
WR
High after Falling Edge of
EXCLK
330
T1 +
T2
ns
TDCK
Data setup before Falling Edge of
EXCLK
50
ns
T1, T2
Minimum Period
500
ns
NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode.
NOTE: Asserting ALE,
CS
, and
RD
or
WR
concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
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