參數(shù)資料
型號： 73M1906B-IVTR/F
廠商： Maxim Integrated Products
文件頁數(shù)： 37/88頁
文件大?。?/td> 0K
描述： MICRODAA SET FXO OF VOIP 20TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,000
系列： *
73M1866B/73M1966B Data Sheet
DS_1x66B_001
42
Rev. 1.6
7.3
Power Management
The 73M1x66B supports three modes of power control for the device.
Normal mode
The 73M1x66B operates normally.
ENFEH = 0
In this mode the Host Side of the Barrier interface is disabled and the
line side device is disabled. The Host side continues to operate
normally.
Sleep mode
The device PLL is turned off and PCLK is propagated on the clock
tree. The PCM DX and
TSC outputs are tri-stated. Control and status
registers of the Host side maintain their content.
Power Down
The device is shut down altogether. The registers remain accessible
through the SPI. Control and status registers of the Host side maintain
their content. To restart the PCM operations, the PCODE register
must be set for the appropriate PCLK frequency value.
In all reduced power modes of operation the SPI interface remains active.
Function
Mnemonic
Register
Location
Type
Description
ENFEH
0x0F[7]
W
Enable Front End Host
1 = Enable Front End of the 73M1906B Host-Side Device. (Default)
0 = Disable Front End of the 73M1906B Host-Side Device.
PWDN
0x0F[6]
W
Power Down Mode
0 = Disable Power Down Mode. (Default)
1 = Enable Power Down Mode.
SLEEP
0x0F[5]
W
Sleep Mode
0 = Disable Sleep Mode. (Default)
1 = Enable Sleep Mode.
7.4
Device Clock Management
Function
Mnemonic
Register
Location
Type
Description
FRCVCO
0x0E[7]
W
Force VCO
0 = The system clock is the same as PCLK. (Default)
1 = The system clock is derived from locked PLL. This is set to 0
upon reset, Sleep or Power Down mode enabled.
LOKDET
0x0D[7]
R
Phase Locked Loop Lock Detect
0 = PLL is not locked. (Default)
1 = PLL is locked to PCLK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
73M1906-IVT/F 制造商:TERIDIAN 功能描述:
73M1912-IM/F 功能描述:電信線路管理 IC MicroDAA Chip Set Line Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1912-IMR/F 功能描述:電信線路管理 IC MicroDAA Chip Set Line Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1912-IVT/F 功能描述:電信線路管理 IC MicroDAA Chip Set Line Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1912-IVTR/F 功能描述:電信線路管理 IC MicroDAA Chip Set Line Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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