參數(shù)資料
型號: 73M2921
廠商: Electronic Theatre Controls, Inc.
英文描述: Advanced Single Chip Modem
中文描述: 先進的單芯片調(diào)制解調(diào)器
文件頁數(shù): 8/41頁
文件大?。?/td> 222K
代理商: 73M2921
73M2921
Advanced Single
Chip Modem
Page 8 of 41
TDK Semiconductor
February 99 Rev M
as to internal RAM are performed through these four bytes of memory (see Table 1).
There are 5 separate types of register access possible through the microcontroller interface. These are:
1.
Access to CR0.
2.
Configuration register access (CR1, CR2), via the Mailbox.
3.
Access to the 8-bit General register set via the Mailbox.
4.
Unsolicited Response status, via the Mailbox.
5.
Memory Block Transfer, via the Mailbox (Not described in this document, please refer to application note
“Using the Mailbox on the 73M2921”).
The host controller initiates all communications over the data bus by sending a command to either read or write to
a location. CR0 is a special case in that it is accessed directly by way of the address bits and does not generate
a response from the 73M2921. All other registers are accessed indirectly by way of a “mailbox” register and will
generate a response from the 73M2921.
UA [1:0]
0 0
0 1
1 0
1 1
ADDRESS
0
1
2
3
DESTINATION/SOURCE
Direct hardware control of CR0 (MSB)
Direct hardware control of CR0 (LSB)
Mailbox function – Control Byte/High Byte
Mailbox function – Data Byte/Low Byte
Write Only
Write Only
Read/Write
Read/Write
Table 1
– Interface Register Address
(1) CONTROL REGISTER CR0 DESCRIPTION
Control Register 0 (CR0) is a 16 bit register that defines functions of general importance to the modem system.
CR0 can be written to directly from the microcontroller interface, and is read/write accessible by the internal DSP.
Control of a number of DSP functions is accomplished by writing two 8 bit bytes to this 16 bit wide register. UA
Address 00b accesses bits D15 through D8 and address 01b is for bits D7 through D0. Writing to these locations
directly access CR0. Writing to the CR0 Register sets an internal bit notifying the internal DSP firmware that the
host microcontroller has issued a command. Access to CR0 does not return a response to the host controller.
Table 2 shows the state of CR0 after various reset conditions. Note that a reset from the register bit D3 (Reset
Chip) does not alter the power-up source mask bit D2 and D1 and they remain unchanged from the previous state
(U = unchanged).
CONDITION
D1
5
1
D1
4
1
D1
3
1
D1
2
1
D1
1
1
D1
0
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset from
Reset Pin
1
0
1
0
1
1
0
0
0
1
Reset from
CR0 bit D3
1
1
1
1
1
1
1
0
1
0
1
1
0
U
U
1
Table 2 - CR0 State After Reset
State of CR0 after reset from the reset pin and CR0 Reset bit (U = unchanged from previous state)
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