參數(shù)資料
型號(hào): 73S1209F-68IMR/F
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: POWER SUPPLY MANAGEMENT CKT, QCC68
封裝: LEAD FREE, QFN-68
文件頁數(shù): 43/123頁
文件大?。?/td> 1385K
代理商: 73S1209F-68IMR/F
73S1209F Data Sheet
DS_1209F_004
MPU Clock Control Register (MPUCKCtl): 0xFFA1
0x0C
Table 13: The MPUCKCtl Register
MSB
LSB
MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0
Bit
Symbol
Function
MPUCKCtl.7
MPUCKCtl.6
MPUCKCtl.5
MDIV.5
This value determines the ratio of the MPU master clock frequency to
the VCO frequency (MCLK) such that
MPUClk = MCLK/(2 * (MPUCKDiv(5:0) + 1)).
Do not use values of 0 or 1 for MPUCKDiv(n).
Default is 0Ch to set CPCLK = 3.6923MHz.
MPUCKCtl.4
MDIV.4
MPUCKCtl.3
MDIV.3
MPUCKCtl.2
MDIV.2
MPUCKCtl.1
MDIV.1
MPUCKCtl.0
MDIV.0
The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce
oscillator configuration. Each side of the crystal should include a 22pF capacitor to ground for both
oscillator circuits and a 1M resistor is required across the 12MHz crystal.
The CPU clock is available as an output on pin CPUCLK (68-pin version only).
73S1209F
X12IN
X12OUT
12MHz
22pF
1M
Ω
Note: The crystal should be placed as close as possible to the IC, and vias should be avoided.
Figure 4: Oscillator Circuit
26
Rev. 1.2
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