參數(shù)資料
型號(hào)： 73S1215F-44IMR/F/P
廠商： Maxim Integrated Products
文件頁數(shù)： 131/136頁
文件大?。?/td> 0K
描述： IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： 73S12xx
核心處理器： 80515
芯體尺寸： 8-位
速度： 24MHz
連通性： I²C，智能卡，UART/USART，USB
外圍設(shè)備： LED，POR，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
73S1215F Data Sheet
DS_1215F_003
94
Rev. 1.4
STX Data Register (STXData): 0xFE07
0x00
Table 87: The STXData Register
MSB
LSB
STXDAT.7 STXDAT.6 STXDAT.5 STXDAT.4 STXDAT.3 STXDAT.2 STXDAT.1 STXDAT.0
Bit
Function
STXData.7
Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by
the hardware and sent to the selected smart card. When the MPU reads this register,
the byte pointer is changed to effectively “read out” the data. Thus, two reads will
always result in an “empty” FIFO condition. The contents of the FIFO registers are not
cleared, but will be overwritten by writes.
STXData.6
STXData.5
STXData.4
STXData.3
STXData.2
STXData.1
STXData.0
SRX Control/Status Register (SRXCtl): 0xFE08
0x00
This register is used to monitor reception of data from the smart card.
Table 88: The SRXCtl Register
MSB
LSB
BIT9DAT
–
LASTRX
CRCERR
RXFULL
RXEMTY
RXOVRR PARITYE
Bit
Symbol
Function
SRXCtl.7
BIT9DAT
Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain
the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK) rising
edge. This is used to read data in synchronous 9-bit formats.
SRXCtl.6
–
SRXCtl.5
LASTRX
Last RX Byte – User sets this bit during the reception of the last byte. When
byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1
mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is
asserted.
SRXCtl.4
CRCERR
(Read only) 1 = CRC (or LRC) error has been detected.
SRXCtl.3
RXFULL
(Read only) RX FIFO is full. Status bit to indicate RX FIFO is full.
SRXCtl.2
RXEMTY
(Read only) RX FIFO is empty. This is only a status bit and does not generate
a RX interrupt.
SRXCtl.1
RXOVRR
RX Overrun – (Read Only) Asserted when a receive-over-run condition has
occurred. An over-run is defined as a byte was received from the smart card
when the RX FIFO was full. Invalid data may be in the receive FIFO. Firmware
should take appropriate action. Cleared when read. Additional writes to the
RX FIFO are discarded when a RXOVRR occurs until the overrun condition is
cleared. Will generate RXERR interrupt.
SRXCtl.0
PARITYE
Parity Error – (Read only) 1 = The logic detected a parity error on incoming
data from the smart card. Cleared when read. Will generate RXERR interrupt.
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