參數(shù)資料
型號: 73S1217F-68IM/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 64/93頁
文件大小: 0K
描述: IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 管件
UG_12xxF_016
73S12xxF Software User Guide
Rev. 1.50
67
4.2.17 Boot Loader and Passcode Management – Available with the LAPI-*BL.lib Only
The Boot Loader code occupies the first (lower) 512 bytes of the Flash program space (0x0000 - 0x01FF)
including the passcode storage space. The Boot Loader assumes that the CPU is running at the default
clock rate which is 3.69 MHz. As a result, the serial baud rate and all soft-timers (timer 0) are calculated
based on the default CPU clock rate. The Boot Loader also only accepts Intel Hex files via the Serial
RS-232 interface. The Boot Loader and Passcode Management API include:
For security and authorization enforcement, the passcode is implemented, embedded and validated
within the Boot Loader code. The Boot Loader will return a hardware error if Security Mode 0 or Security
Mode 1 has already been enabled. Figure 9 depicts a successful Boot Loader scenario.
Application
Layer
LAPI
Invoke the Boot
Loader Code
Boot (U16 PassCode
)
Send Intel Hex record
(one record at a time
) in the format of:
:NNAAAARRDD
..DD.CRC<crlf>
NN=#of bytes in record
, AAAA = address
of first byte,
RR=record type - see
Note2
'P' = pass (record
is valid) OR 'F'
= fail
Validate PassCode
and wait for
Intel hex record
Start
Flash
Prog.
Start
Flash
Down
Load
If response = 'F'
resend the record,
ifresponse = 'P'
send next record
Figure 9: Boot Loader Scenario
The Passcode is a 2-byte integer data type where the second byte is the complement of the first byte.
After validating the Passcode, the LAPI will configure the device’s serial interface to be running at 115200
baud with 8 data bits, No stop bit and Xon/Xoff control enabled. It then waits for a valid Intel hex
record from the Serial RS-232 interface. The record’s checksum is checked along with its Flash address
location. The Boot Loader code area (the first page of Flash – 512 bytes at address 0x0000 – 0x01FF)
will be protected. Any hex record with addresses on the first page will be ignored. Once a valid hex
record is accepted by the device, all Flash space (except for the Boot Loader area) will be permanently
erased. For each successful hex record received by the device, the device will respond with a ‘P’. For
each failed hex record received by the device (bad CRC), the device will respond with an ‘F’. When the
device receives the last successful hex record and if there is no error, the device will immediately jump to
the start of the new application. For a sample of the usage of the Boot Loader API, review the
Pseudo-CCID application code (built and shipped in a separate TSC 73S12xxF PCCID Serial release).
Figure 10 illustrates the Flash Download and Flash Programming process.
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