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參數(shù)資料
| 型號： | 74AC11833 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit To 9-Bit Parity Bus Transceivers(8位-9位奇偶總線接收傳送器) |
| 中文描述： | 8位到第9位奇偶總線收發(fā)器（8位-9位奇偶總線接收傳送器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 74AC11833 |
54AC11833, 74AC11833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCAS387 – MARCH 1990–REVISED OCTOBER 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
High-Speed Bus Transceivers With Parity
Generator/Checker
Parity-Error-Flag Open-Drain Output
Register for Storage of the Parity-Error Flag
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
500-mA Typical Latch-Up Immunity at
125
°
C
Package Options Include Plastic “Small
Outline” Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
description
The
′
AC11833 is an 8-bit to 9-bit parity transceiver
designed for two-way communication between
data buses. When data is transmitted from the A
bus to the B bus, a parity bit is generated. When
data is transmitted from the B bus to the A bus with
its corresponding parity bit, the ERR output will
indicate whether or not an error in the B data has
occurred. The output enable inputs OEA and OEB
can be used to disable the device so that the
buses are effectively isolated.
A 9-bit parity generator/checker generates a
parity-odd output (PARITY) and monitors the
parity of the I/O ports with an open-drain parity
error flag (ERR). ERR is clocked into the register
on the rising edge of the CLK input. The error flag
register is cleared with a low pulse on the CLR
input. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and
inverted parity is generated. Inverted parity is a
forced error condition that gives the designer
more system diagnostic capability.
The 54AC11833 is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The 74AC11833 is characterized for
operation from –40
°
C to 85
°
C.
EPIC is a trademark of Texas Instruments Incorporated.
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PARITY
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
ERR
OEA
OEB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLR
CLK
11833 . . . JT PACKAGE
11833 . . . DW OR NT PACKAGE
(T0P VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
B7
B8
CLR
CLK
ERR
A8
A7
B1
OEB
OEA
PARITY
A1
A2
A3
4
26
14 15 16 1718
A
G
G
G
G
A
A
B
B
B
V
B
B
11833 . . . FK PACKAGE
(T0P VIEW)
V
C
P
相關PDF資料 |
PDF描述 |
|---|---|
| 74AC11881 | Arithmetic Logic Units/Fuction Generators(算術(shù)邏輯單元/函數(shù)發(fā)生器) |
| 74AC11B | TRIPLE 3-INPUT AND GATE |
| 74AC11 | TRIPLE 3-INPUT AND GATE |
| 74AC11M | TRIPLE 3-INPUT AND GATE |
| 74AC11MTC | Triple 3-Input AND Gate |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74AC11833DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-Bit Inverting Bus Transceiver |
| 74AC11833NT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-Bit Inverting Bus Transceiver |
| 74AC11853DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
| 74AC11853NT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
| 74AC11873 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS |
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