參數(shù)資料
型號(hào): 74AC11833
廠商: Texas Instruments, Inc.
英文描述: 8-Bit To 9-Bit Parity Bus Transceivers(8位-9位奇偶總線接收傳送器)
中文描述: 8位到第9位奇偶總線收發(fā)器(8位-9位奇偶總線接收傳送器)
文件頁(yè)數(shù): 6/8頁(yè)
文件大小: 82K
代理商: 74AC11833
Setup time before CLK
tsu
ns
UNIT
PARAMETER
UNIT
A or B
A
OEA or OEB
OEA or OEB
CLK
CLR
A or B
ERR
ERR
A or B
PARITY
B or A
PARITY
OEA
ns
ns
ns
ns
ns
ns
ns
54AC11833, 74AC11833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Note 1)
TA = 25
°
C
MIN
5
5
5
14
2
0
54AC11833
MIN
5
5
5
14
2
0
74AC11833
MIN
5
5
5
14
2
0
MAX
MAX
MAX
CLK high
CLK low
CLR low
Bi and PARITY
CLR inactive
tw
Pulse duration
ns
th
Hold time after CLK
, Bi and PARITY
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Note 1)
FROM
(INPUT)
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPHL
tPLH
tPLH
tPHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1 of Advanced CMOS Logic Data Book, 1990
TO
TA = 25
°
C
MIN
54AC11833
MIN
74AC11833
MIN
(OUTPUT)
MAX
MAX
MAX
P
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