54ACT11881, 74ACT11881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
description
The ’ACT11881 arithmetic logic unit (ALU)/function generators have a complexity of 77 equivalent gates on a
monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables
1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition,
subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries
must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme
is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs,
G and P, for the four bits in the package. When used in conjunction with the 54ACT11882 or 74ACT11882 full
carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown
previously illustrate the little additional time required for addition of longer words when full carry look-ahead is
employed. The method of cascading ’ACT11882 circuits with these ALUs to provide multilevel full carry
look-ahead is illustrated under signal designations.
If high speed is not of importance, a ripple-carry input (C
n
) and a ripple-carry output (C
n + 4
) are available.
However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths
can be performed without external circuitry.
The ’ACT11881 will accommodate active-high or active-low data if the pin designations are interpreted as
follows:
PIN NUMBER
Active-low data (Table 1)
Active-high data (Table 2)
28
A0
A0
24
B0
B0
27
A1
A1
23
B1
B1
26
A2
A2
20
B2
B2
25
A3
A3
19
B3
B3
4
5
10
F2
F2
11
F3
F3
1
14
Cn+4
Cn+4
12
P
X
13
G
Y
F0
F0
F1
F1
Cn
Cn
Subtraction is accomplished by 1’s complement addition, where the 1’s complement of the subtrahend is
generated internally. The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B.
The ’ACT11881 can also be used as a comparator. The A=B output is internally decoded from the function
outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will
assume a high level to indicate equality (A=B). The ALU must be in the subtract mode with C
n
=H when
performing this comparison. The A=B output is open-collector so that it can be wired-AND connected to give
a comparison for more than four bits. The carry output (C
n + 4
) can also be used to supply relative magnitude
information. Again, the ALU must be placed in the subtract mode by placing the function select input S3, S2,
S1, S0 at L, H, H, L, respectively.
INPUT Cn
OUTPUT Cn 4
OUTPUT Cn+4
ACTIVE-LOW DATA
(FIGURE 1)
A
≥
B
A < B
A > B
A
≤
B
ACTIVE-HIGH DATA
(FIGURE 2)
A
≤
B
A > B
A < B
A
≥
B
H
H
L
L
H
L
H
L
These circuits have been designed to not only incorporate all of the designer’s requirements for arithmetic
operations, but also to provide 16 possible functions of two Boolean variables without the use of external
circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the
mode-control input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables
1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.
The ’ACT11881 has the same pinout and same functionality as the ’ACT11181 except for the P, G, and C
n + 4
outputs when the device is in the logic mode (M = H).