- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369300 > 74ALS09 (Fairchild Semiconductor Corporation) Quad 2-Input AND Gate with Open Collector Outputs PDF資料下載
參數(shù)資料
| 型號： | 74ALS09 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Quad 2-Input AND Gate with Open Collector Outputs |
| 中文描述： | 四2輸入與門與集電極開路輸出 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 69K |
| 代理商： | 74ALS09 |
SN54ALS09, SN74ALS09
QUADRUPLE 2-INPUT POSITIVE-AND GATES
WITH OPEN-COLLECTOR OUTPUTS
SDAS084B – APRIL 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
VOH
VOL
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
≤
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALS1005 | Hex Inverting Drivers with Open Collector Outputs |
| 74ALS191 | SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS |
| 74ALS540 | OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS |
| 74ALS540 | Octal Inverting Buffer and Line Driver with 3-STATE Outputs |
| 74ALS573 | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS1005 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hex Inverting Drivers with Open Collector Outputs |
| 74ALS1034N | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:Texas Instruments 功能描述: |
| 74ALS1035DE4 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 74ALS109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。