參數資料
型號: 74ALVCH16271DLRG4
廠商: Texas Instruments, Inc.
英文描述: 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS
中文描述: 12位至24位復用總線交換具有三態(tài)輸出
文件頁數: 1/15頁
文件大?。?/td> 216K
代理商: 74ALVCH16271DLRG4
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16271 is intended for applications in
which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. This
device
is
particularly
suitable
between
conventional
DRAMs
microprocessors.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
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7
8
9
10
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12
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28
56
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45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017G–JULY 1995–REVISED SEPTEMBER 2004
as
and
an
interface
high-speed
A data is stored in the internal A-to-B registers on the
low-to-high
transition
of
provided that the clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port.
the
clock
(CLK)
input,
Transparent
asynchronous operation to maximize memory access
throughput. These latches transfer data when the
latch-enable (LE) inputs are low. The select (SEL)
line selects 1B or 2B data for the A outputs. Data flow
is controlled by the active-low output enables (OEA,
OEB).
latches
in
the
B-to-A
path
allow
line
To ensure the high-impedance state during power up or power down, the output enables should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
space
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
SN74ALVCH16271DL
SN74ALVCH16271DLR
SN74ALVCH16271DGGR ALVCH16271
TOP-SIDE
MARKING
T
A
PACKAGE
(1)
Tube
Tape and reel
Tape and reel
SSOP - DL
ALVCH16271
-40
°
C to 85
°
C
TSSOP - DGG
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1995–2004, Texas Instruments Incorporated
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