參數(shù)資料
型號(hào): 74ALVCH16903DGVRE4
廠商: Texas Instruments, Inc.
英文描述: 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
中文描述: 3.3 V的12位通用總線驅(qū)動(dòng)器,帶有奇偶校驗(yàn)器和雙三態(tài)輸出
文件頁數(shù): 11/16頁
文件大?。?/td> 213K
代理商: 74ALVCH16903DGVRE4
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V
±
0.3 V
From Output
Under Test
PARI/O
LOAD CIRCUIT
t
PLH
t
PHL
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
V
OH
V
OL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2.5 ns, t
f
2.5 ns.
C. t
PLH
and t
PHL
are the same as t
pd
.
C
L
= 0.6 pF
(see Note A)
Test
Point
PARI/O of
Second
ALVCH16903
C
L
= 0.6 pF
(see Note A)
Z
O
= 52
t
d
= 63 ps
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
R
L
= 10
t
PLH
t
PHL
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
V
OH
V
OL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Test
Point
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2.5 ns, t
f
2.5 ns.
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D–MARCH 1997–REVISED SEPTEMBER 2004
Figure 5. Load Circuit and Voltage Waveforms
Figure 6. Load Circuit and Voltage Waveforms
11
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