參數(shù)資料
型號： 74ALVCH16903DGVRE4
廠商： Texas Instruments, Inc.
英文描述： 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
中文描述： 3.3 V的12位通用總線驅(qū)動(dòng)器，帶有奇偶校驗(yàn)器和雙三態(tài)輸出
文件頁數(shù)： 2/16頁
文件大小： 213K
代理商： 74ALVCH16903DGVRE4
www.ti.com
DESCRIPTION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D–MARCH 1997–REVISED SEPTEMBER 2004
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16903 is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLES
FUNCTION
INPUTS
CLKEN
OUTPUTS
OE
L
L
L
L
L
L
H
MODE
L
L
L
L
H
H
X
CLK
↑
↑
↑
↑
X
X
X
A
H
L
H
L
H
L
X
1Yn
(1)
–8Yn
(1)
H
L
Y
0
Y
0
H
L
Z
9Yn
(1)
–12Yn
(1)
H
L
H
L
H
L
Z
L
L
H
H
X
X
X
(1)
n = 1 or 2
PARITY FUNCTION
INPUTS
OUTPUT
YERR
Σ
OF INPUTS
1A–10A = H
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
X
OE
PAROE
(1)
11A/YERREN
(2)
PARI/O
APAR
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
H
L
L
H
L
H
H
L
H
H
(1)
(2)
When used as a single device, PAROE must be tied high.
Valid after appropriate number of clock pulses have set internal register
PARI/O FUNCTION
(1)
INPUTS
Σ
OF INPUTS
1A–10A = H
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
OUTPUT
PARI/O
PAROE
APAR
L
L
L
L
H
L
L
H
H
X
L
H
H
L
Z
(1)
This table applies to the first device of a cascaded pair of
SN74ALVCH16903 devices.
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74ALVCH16903DGVRG4 功能描述:總線收發(fā)器 3.3V 12B Univ Bus Dr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCH16903DLG4 功能描述:通用總線函數(shù) 3.3V 12B Univ Bus Dr RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCH16903DLRG4 功能描述:總線收發(fā)器 3.3-V 12-Bit Univ Bus Driver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCH16952 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit registered transceiver 3-State
74ALVCH16952DG 功能描述:總線收發(fā)器 16-BIT REG. TRANSCVR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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