參數(shù)資料
型號： 74ALVCH16903DLRG4
廠商： Texas Instruments, Inc.
英文描述： 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
中文描述： 3.3 V的12位通用總線驅(qū)動器，帶有奇偶校驗器和雙三態(tài)輸出
文件頁數(shù)： 6/16頁
文件大小： 213K
代理商： 74ALVCH16903DLRG4
www.ti.com
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1 and
Figure 4)
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 4)
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D–MARCH 1997–REVISED SEPTEMBER 2004
V
CC
= 2.5 V
±
0.2 V
MIN
V
CC
= 3.3 V
±
0.3 V
MIN
V
CC
= 2.7 V
UNIT
MAX
125
MIN
MAX
125
MAX
125
f
clock
t
w
Clock frequency
Pulse duration, CLK
↑
MHz
ns
3
3
3
1A–12A before CLK
↑
1A–10A before CLK
↑
Register mode
Buffer mode
Register mode
Buffer mode
Both modes
Buffer mode
Register mode
Register mode
Buffer mode
Register mode
Buffer mode
Register mode
Buffer mode
Buffer mode
Register mode
1.7
5.9
1.2
4.6
2.4
1.9
5.2
1.5
3.6
1.45
4.4
1.3
3.1
1.7
1.6
2.2
0.55
0.25
0.7
0.25
0.4
0.5
0.4
0.4
APAR before CLK
↑
t
su
Setup time
ns
PARI/O before CLK
↑
11A/YERREN before CLK
↑
CLKEN before CLK
↑
1A–12A after CLK
↑
1A–10A after CLK
↑
2
2
1.9
2.6
0.25
0.25
0.4
0.25
0.25
0.25
0.25
0.5
2.5
0.4
0.25
0.7
0.25
0.25
0.25
0.25
0.25
APAR after CLK
↑
t
h
Hold time
ns
PARI/O after CLK
↑
11A/YERREN after CLK
↑
CLKEN after CLK
↑
V
CC
= 2.5 V
±
0.2 V
MIN
125
1
1
1.2
1
1
1
1
1.1
1
1
1
1
1.2
V
CC
= 3.3 V
±
0.3 V
MIN
125
1.1
1.4
1.7
1.3
1.3
1.2
1.2
1.4
1
1.7
1.2
1.9
1.5
V
CC
= 2.7 V
FROM
(INPUT)
TO
PARAMETER
UNIT
(OUTPUT)
MAX
MIN
125
MAX
MAX
f
max
MHz
Buffer mode
A
Y
4.4
5.7
8.6
6.8
5.9
6.1
5.9
6.5
5.6
6.4
3.2
3.6
5.1
4.2
4.9
7.9
5.2
5.8
5.5
4.9
6.4
3.8
4.4
6.6
4.5
4.9
4.8
4.6
5.4
4.8
t
pd
YERR
PARI/O
PARI/O
Y
ns
Both modes
CLK
t
pd(1)
t
pd
t
PLH
t
PHL
Both modes
Both modes
CLK
MODE
ns
ns
Register mode
CLK
Y
ns
OE
Y
t
en
Both modes
ns
PAROE
OE
PAROE
PARI/O
Y
PARI/O
6
5.2
3.8
4.2
4.9
5
t
dis
Both modes
ns
3.8
t
PLH
t
PHL
4
Both modes
OE
YERR
ns
4.2
(1)
See Figure 2 and Figure 5 for the load specification.
6
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