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參數(shù)資料
| 型號： | 74GTL1655ATTR |
| 廠商： | 意法半導體 |
| 英文描述： | 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION |
| 中文描述： | 16位LVTTL差動的GTL /的GTL通用總線收發(fā)器與帶電插入 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 260K |
| 代理商： | 74GTL1655ATTR |
ObsoeePoduc(s ObsoeePoduc(s
41
V
49, 51, 52, 54, 55, 56, 58, 59
2A1 to 2A8
61
V
ERC
62, 63
1LEBA, 1LEAB
64
CLK
5, 8, 10, 12, 18, 21, 24, 26, 30,
39, 44, 47, 53, 57, 60
3, 15, 28, 50
V
CC
74GTL1655A
2/16
controlled by output-enable (OEAB and OEBA),
latch-enable (LEAB and LEBA), and clock (CLK)
inputs. For A-to-B data flow, the devices operate
in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLK is held at
a high or low logic level. If LEAB is low, the A data
is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in
the high-impedance state. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA,
and CLK. The output enable (OE) is used to
disable both ports simultaneously.
Active bus-hold circuitry is provided on the A port
to hold unused or floating data inputs at a valid
logic level. When V
CC
is between 0 and 1.5 V, the
device is in the high-impedance state during
power up or power down. However, to ensure the
high-impedance state above 1.5V, OE should be
tied to V
CC
through a pull-up resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
All input and output are equipped with protection
circuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage.
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N
°
SYMBOL
NAME AND FUNCTION
1, 2
1OEAB, 1OEBA
1A1 to 1A8
2A1 to 2A8
2OEAB, 2OEBA
OE
2LEBA, 2LEAB
BIAS V
CC
2B8 to 2B1
Output Enable Input
Data Inputs/Outputs LVTTL
Data Inputs/Outputs LVTTL
Output Enable Input
Output Enable Input
Latch Enable
Pre-Charge Supply Voltage
Data Inputs/Outputs GTL/GTL+
GTL Voltage Reference Input
Data Inputs/Outputs GTL/GTL+
Edge Rate Control
Latch Enable
Clock Input (LOW to HIGH edge triggered)
Ground (0V)
4, 6, 7, 9, 11, 13, 14, 16
17, 19, 20, 22, 23, 25, 27, 29
31, 32
33
34, 35
36
37, 38, 40, 42, 43, 45, 46, 48
GND
Positive Supply Voltage
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74GTL1655TTR | 功能描述:總線收發(fā)器 16-Bit Bus Transcvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74GTL16612DGGRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL-GTL/GTL Univ Bus Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74GTL16612DGGRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL-to-GTL/GTL Univ Bus Xceivers RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74GTL16616DGGRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 17B LVTTL-GTL/GTL Univ Bus Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74GTL16616DGGRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 17B LVTTL-To-GTL/GTL Univ Bus Xceivers RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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