參數(shù)資料
型號(hào)： 74GTLP2033DGVRE4
廠商： Texas Instruments, Inc.
英文描述： 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述： 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開登記LVTTL港口及反饋路徑
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 367K
代理商： 74GTLP2033DGVRE4
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C
–
JUNE 2001
–
REVISED SEPTEMBER 2001
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tPLH
tPHL
tPLH
tPHL
LOOPBACK
AO
2.5
6.2
6.2
ns
–
2
5
5
AI
AO
1
5.6
5.6
ns
(loopback high)
–
1
5
5
Rise time B port outputs (20% to 80%)
Rise time, B-port outputs (20% to 80%)
Slow
2.8
tr
Fast
1.5
ns
Rise time, AO (10% to 90%)
3.5
Fall time B port outputs (80% to 20%)
Fall time, B-port outputs (80% to 20%)
Slow
3
tf
Fast
1.8
1.5
ns
Fall time, AO (90% to 10%)
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
°
C.
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
§
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
AI
B
Slow
0.5
1
ns
0.5
1
AI
B
Fast
0.4
0.9
ns
0.4
0.9
CLKAB/LEAB
B
Slow
0.5
1
ns
0.5
1
CLKAB/LEAB
B
Fast
0.4
0.9
ns
0.4
0.9
AI
B
Slow
1.4
2
tk(t)
Fast
0.6
1.4
ns
tsk(t)
CLKAB/LEAB
B
Slow
1.8
2.5
Fast
0.9
1.8
Slow (ERC = L) and Fast (ERC = H)
All typical values are at VCC = 3.3 V, TA = 25
°
C.
§
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
tsk(LH)/tsk(HL) and tsk(t)
–
Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
相關(guān)PDF資料
PDF描述
74GTLP22034DGGRE4 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
74GTLP22034DGVRE4 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
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74H76 Cardmaster Enclosure; NEMA Type:4X; Enclosure Material:Polycarbonate; External Height:4.2"; External Width:6.3"; External Depth:6.5"; Enclosure Color:Light Gray; Approval Bodies:UL, cUL; Cover Color:Smoked Transparent
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