參數(shù)資料
型號(hào): 74GTLP2033DGVRE4
廠商: Texas Instruments, Inc.
英文描述: 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述: 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開(kāi)登記LVTTL港口及反饋路徑
文件頁(yè)數(shù): 15/20頁(yè)
文件大小: 367K
代理商: 74GTLP2033DGVRE4
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C
JUNE 2001
REVISED SEPTEMBER 2001
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
TYP
UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
AI
B
Slow
4.7
ns
(buffer)
5
AI
B
Fast
3.7
ns
(buffer)
4
LEAB
B
Slow
5.5
ns
(latch mode)
5.8
LEAB
B
Fast
4.6
ns
(latch mode)
4.8
CLKAB
B
Slow
5.8
ns
(flip-flop mode)
6
CLKAB
B
Fast
4.9
ns
(flip-flop mode)
4.9
OMODE
B
Slow
5.5
ns
5.7
OMODE
B
Fast
4.5
ns
4.7
tr
Rise time B port outputs (20% to 80%)
Rise time, B-port outputs (20% to 80%)
Slow
1.8
ns
Fast
1.1
tf
Fall time B port outputs (80% to 20%)
Fall time, B-port outputs (80% to 20%)
Slow
Fast
3.4
2.6
ns
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
°
C. All values are derived from TI-SPICE models.
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74GTLP22034DGGRE4 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
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74H76 Cardmaster Enclosure; NEMA Type:4X; Enclosure Material:Polycarbonate; External Height:4.2"; External Width:6.3"; External Depth:6.5"; Enclosure Color:Light Gray; Approval Bodies:UL, cUL; Cover Color:Smoked Transparent
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