參數(shù)資料
型號(hào): 74GTLP22034DGGRE4
廠商: Texas Instruments, Inc.
英文描述: 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述: 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開登記LVTTL港口及反饋路徑
文件頁數(shù): 2/20頁
文件大小: 366K
代理商: 74GTLP22034DGGRE4
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C
JUNE 2001
REVISED SEPTEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP22034 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports,
Texas Instruments GTLP Frequently Asked Questions
,
literature number SCEA019, and
GTLP in BTL Applications
, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times.
This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to V
CC
through a pullup resistor
and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
terminal assignments
1
2
3
4
5
6
A
IMODE1
NC
NC
NC
NC
IMODE0
B
AO1
AI1
GND
GND
BIAS VCC
OEAB
B1
C
AO2
AI2
VCC
GND
ERC
B2
D
E
F
AO3
AI3
GND
OEAB
B3
AO4
AI4
CLKAB/LEAB
B4
AO5
AI5
CLKBA/LEBA
B5
G
AO6
AI6
GND
GND
OEBA
B6
H
AO7
AI7
VCC
GND
VCC
GND
LOOPBACK
B7
J
AO8
AI8
VREF
NC
B8
K
OMODE0
NC
NC
NC
OMODE1
NC = No internal connection
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
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