參數(shù)資料
型號(hào)： 74GTLP22034DGGRE4
廠商： Texas Instruments, Inc.
英文描述： 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述： 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開(kāi)登記LVTTL港口及反饋路徑
文件頁(yè)數(shù)： 3/20頁(yè)
文件大小： 366K
代理商： 74GTLP22034DGGRE4
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C
–
JUNE 2001
–
REVISED SEPTEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP
–
DGG
Tape and reel
SN74GTLP22034DGGR
GTLP22034
–
40
°
C to 85
°
C
TVSOP
–
DGV
Tape and reel
SN74GTLP22034DGVR
GT22034
VFBGA
–
GQL
Tape and reel
SN74GTLP22034GQLR
GS034
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLP22034 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type
latches and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data
transmission is true, with AI data going to the B port and B data going to AO. The split LVTTL AI and AO provides
a feedback path for control and diagnostics monitoring.
The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,
OMODE1 and OMODE0 for A to B) inputs as a buffer, a D-type flip-flop, or a D-type latch. When configured in
the buffer mode, the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge
of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve as
active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element is the B-to-A input.
The AO enable/disable control is provided by OEBA. When OEBA is low or when V
CC
is less than 1.5 V, AO
is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).
The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or V
CC
is less than 1.5 V, the B port
is inactive. If OEAB is high and OEAB is low, the B port is active.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO) or inactive (B port) states.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74GTLP22034DGGRG4 功能描述:特定功能邏輯 8B LVTTL-GTLP Adj- Edge-Rate Reg Xceivr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
74GTLP22034DGVRE4 功能描述:特定功能邏輯 8B LVTTL-GTLP Adj- Edge-Rate Reg Trans RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
74GTLP22034DGVRG4 功能描述:特定功能邏輯 8B LVTTL-GTLP Adj- Edge-Rate Reg Trans RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
74GTLPH1612DGGRE4 功能描述:轉(zhuǎn)換 - 電壓電平 18-Bit LVTTL/GTLP Univ Bus Xcvr RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
74GTLPH1612DGGRG4 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL-GTLP Adj- Edge-Rate Univ Bus RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
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