參數(shù)資料
型號: 74LV74PW,118
廠商: NXP Semiconductors
文件頁數(shù): 2/19頁
文件大?。?/td> 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74LV
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 56MHz
觸發(fā)器類型: 正邊沿
輸出電流高,低: 12mA,12mA
電源電壓: 1 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
74LV74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 9 September 2013
10 of 19
NXP Semiconductors
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 6.
Clock pulse (nCP) to output (nQ, nQ) propagation delays, nCP pulse width and maximum frequency
aaa-008840
GND
VI
GND
VI
VOH
VOL
nCP input
nQ output
nD input
tsu
tPLH
tPHL
VM
tW
tPHL
VM
th
tsu
1/fmax
tPLH
th
Measurement points are given in Table 8.
Fig 7.
The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRD to nCP recovery time
trec
VM
aaa-008842
tPHL
tPLH
tPHL
tPLH
tW
VM
VI
VOH
VOL
VOH
VM
GND
nCP input
nSD input
nRD input
nQ output
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