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參數(shù)資料
| 型號(hào)： | 74LVC1G57GV,125 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG MULTI-FUNC GATE SC-74 |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74LVC |
| 邏輯類型： | 可配置多功能 |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 3 |
| 施密特觸發(fā)器輸入： | 是 |
| 輸出類型： | 單端 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74，SOT-457 |
| 供應(yīng)商設(shè)備封裝： | 6-TSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 840 (CN2011-ZH PDF) |
| 其它名稱： | 568-4835-6 |
CS35L01/03
18
DS909F1
5.3.3
Output Filter Power Dissipation Considerations
In systems without inductive series elements like inductors or ferrite beads, power losses in the output
filter are equal to the switching losses that occur in the system due to the cyclical charging and discharging
of capacitors connected to the amplifier outputs. In systems that require an inductive series element, con-
ducted losses also occurs due to the series impedance added to the output path.
5.3.3.1
Conduction Losses for All modes of Operation
For all modes of operation (SD, FSD, HD, and FHD) of the CS35L01/03, the conduction losses are gov-
erned by the equation:
Where:
P
= Power dissipated in the series impedance.
I
= RMS AC output current
Z
= impedance of the series element at the frequency of the AC current
This equation neglects any series impedances presented by the PCB traces or speaker wires in the output
path.
5.3.3.2
Switching Losses in SD/FSD Mode
Switching losses in SD/FSD Mode are governed by the equation
Where:
P
= Power dissipated in the capacitor (neglecting parasites).
C
= Value of filtering capacitor
V
= Peak voltage developed across the capacitor
f
= Switching frequency of the outputs
These calculations are straightforward, as the peak voltage is simply the voltage level attached to VBATT,
the capacitor is the value of capacitor that has been added for filtering (neglecting parasitic board capac-
itances), and the frequency is 192 kHz or 76 kHz for SD and FSD, respectively.
5.3.3.3
Switching Losses in HD/FHD.
Many factors affect the switching losses when the device is operated in HD/FHD mode. These factors in-
clude the frequency of the content being amplified, the voltage level of VBATT, and the amplitude of the
output signal will factor into both the voltage presented across the capacitors and the frequency at which
the capacitors are charged or discharged.
Static signals (i.e. sine waves at a fixed amplitude) are easier to consider than are dynamic signals (i.e.
musical content), as they are governed by the same equation as that listed in Section 5.3.3.1 and Section
5.3.3.2 on page 18. Modifications to that equation are limited to the voltage term (V) and the frequency
term (f), depending on whether the static input signal amplitude is causing the output devices to switch at
76 kHz or 192 kHz, and to operate off of the VBATT supply or off of the internally generated LDO.
PI2Z
=
P
1
2
---CV2f
=
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| 74LVC1G57GW | 制造商:NXP Semiconductors 功能描述:IC CONFIG MULTI-FUNC GATE XSON6 制造商:NXP Semiconductors 功能描述:IC, CONFIG MULTI-FUNC GATE, XSON6 制造商:NXP Semiconductors 功能描述:IC, CONFIG MULTI-FUNC GATE, XSON6, Logic Type:Configurable Multiple Function, Output Current:32mA, No. of Inputs:3, Supply Voltage Min:1.65V, Supply Voltage Max:5.5V, Logic Case Style:SOT-363, No. of Pins:6, Operating Temperature , RoHS Compliant: Yes |
| 74LVC1G57GW,125 | 功能描述:邏輯門 3.3V LP CONFIG GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVC1G57GW125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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