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參數(shù)資料
| 型號(hào)： | 74LVC1G57GV,125 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG MULTI-FUNC GATE SC-74 |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74LVC |
| 邏輯類型： | 可配置多功能 |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 3 |
| 施密特觸發(fā)器輸入： | 是 |
| 輸出類型： | 單端 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74，SOT-457 |
| 供應(yīng)商設(shè)備封裝： | 6-TSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 840 (CN2011-ZH PDF) |
| 其它名稱： | 568-4835-6 |
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CS35L01/03
DS909F1
19
It is important to note that the HD and FHD modes offer significant improvement over traditional Class-D
in idle power dissipation when an external output filter is necessary. This is because the voltage term (V)
is significantly reduced in HD and FHD mode. As can be seen in the equation, this is notable because
reduction in the operating voltage reduces power losses not linearly, but instead exponentially- due to the
voltage squared term (V2). It is also notable that when operated at high output levels, FHD modes also
offers unique improvement in output filter losses, due to reducing the switching frequency (f) at higher out-
put levels.
5.4
Power-Up and Power-Down
When pulled to a logic low state, the SD pin tristates the outputs and shuts down the CS35L01/03 device,
putting it into a low power mode.
5.4.1
Recommended Power-Up Sequence
1. With the SD pin pulled low, apply power to the CS35L01/03 and wait for the power supply to be stable.
2. Set the SD pin high to begin normal operation.
5.4.1.1
Zero-Crossing on Power-Up Functionality
The CS35L01/03 implements an input-signal zero-crossing detection function that is enabled during pow-
er-up. This function is designed to prevent audible artifacts and eliminate any need to mute the amplifier’s
input audio signal during the power-up process.
After a minimum start-up time of tstart, the CS35L01/03 will begin to detect input-signal zero-crossings.
The amplifier will then enable its switching outputs at the time of the first detected input-signal zero-cross-
ing transition. If no input-signal zero-crossing is detected before ttimeout, the zero-crossing function will tim-
eout and the outputs will begin switching immediately.
5.4.2
Recommended Power-Down Sequence
1. Mute the audio supplied to the CS35L01/03.
2. Pull the SD pin low in order to reset the device and put it into the low power mode.
3. The power supply to the CS35L01/03 can now be removed.
OUT+/-
Shut-Down /
Low Power
Mode
tstart
SD
VIH
Device Ready:
Waiting for Zero
Crossing Input
Signal or ttimeout
Internal
Start-Up
VIL
PWM OUT+/-
Active
VBATT or VLDO
IN+/-
ttimeout
Figure 6. Power-Up Timing with Input
Zero-Crossing
Figure 7. Power Up Timing without Input
Zero-Crossing
OUT+/-
Shut-Down /
Low Power
Mode
tstart
SD
VIH
Device Ready: Waiting for Zero
Crossing Input Signal or ttimeout
Internal
Start-Up
VIL
PWM OUT+/-
Active
VBATT or VLDO
IN+/-
ttimeout
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| 74LVC1G57GW,125 | 功能描述:邏輯門 3.3V LP CONFIG GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVC1G57GW125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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