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參數(shù)資料
| 型號： | 7536 |
| 英文描述： | Low Quiescent Current LDO, -40C to +125C, 3-SOT-23, T/R |
| 中文描述： | 7536組數(shù)據(jù)表數(shù)據(jù)表660K/SEP.05.00 |
| 文件頁數(shù)： | 29/46頁 |
| 文件大小： | 660K |
| 代理商： | 7536 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7536 Group
MITSUBISHI MICROCOMPUTERS
28
Serial I/O2 operation
By writing to the serial I/O2 register(address 0031
16
) the serial I/O2
counter is set to
“
7
”
.
After writing, the S
DATA
pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the S
DATA
pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
Serial I/O2 counter is cleared to
“
0
”
.
Transfer clock stops at an
“
H
”
level.
Interrupt request bit is set.
Shift completion flag is set.
Also, the S
DATA
pin is in a high impedance state after the data trans-
fer is complete (refer to figure 31).
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the S
DATA
pin is not in a high impedance state on the completion
of data transfer.
Fig. 31 Serial I/O2 timing (LSB first)
D
0
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
S
at serial I/O2
input receive
S
at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Note
:
When the internal clock is selected as the transfer and the direction register of P1
3
/S
DATA
pin is set to the input mode,
the S
DATA
pin is in a high impedance state after the data transfer is completed.
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