參數(shù)資料
型號(hào)： 7805ALPRPDB
廠商： MAXWELL TECHNOLOGIES
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封裝： RAD-PAK, DIP-28
文件頁(yè)數(shù)： 10/34頁(yè)
文件大小： 605K
代理商： 7805ALPRPDB
Memory
PRELIMINARY
18
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
1
Offset Binary Coding.
Power Down
PD
0
Complete power-down of device.
1
Normal operation (default on power-up).
System Standby
SSTBY
0
Normal operation.
1
All DACs in the package put in standby mode (defaulton power-up).
System Clear
SCLR
0
Normal operation.
1
All DACs in the package are cleared to a known state depending on the coding scheme selected. The SCLR
bit clears the Main DACs only; the Sub DACs are unaffected by the system clear function. The main DAC is
cleared to different levels depending on the coding scheme. With offset binary coding the Main DAC output is
cleared to the bottom of the transfer function VBIAS/16. With twos complement coding the Main DAC output
is cleared to midscale VBIAS. The channel output will be the sum of the Main DAC and Sub DAC contribu-
tions.
7805ALP CHANNEL CONTROL REGISTER
This register allows the user to have control over individual DACs in the package. The control bits in this register
include multiplexer output selection (MX1 and MX0), Main or Sub DAC selection (MAIN/SUB), standby (STBY) and
individual DAC clear (CLR). The function of these bits is as follows.
Multiplexer Selection (MX1, MX0)
Table 19 shows the VBIAS selection using MX1 and MX0 bits in the channel control register.
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