參數(shù)資料
型號(hào): 7805ALPRPDB
廠(chǎng)商: MAXWELL TECHNOLOGIES
元件分類(lèi): ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封裝: RAD-PAK, DIP-28
文件頁(yè)數(shù): 32/34頁(yè)
文件大?。?/td> 605K
代理商: 7805ALPRPDB
Memory
PRELIMINARY
7
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
FIGURE 1. CONVERSION TIMING WITH OUTPUTS ENABLED AFTER CONVERSION (CS TIED LOW)
0
0
Enables databus with valid data from conversion "n-1". Conversion "n" in
progress."
00
New conversion initiated without acquisition of a new signal. Data will be invalid.
CS and/or R/C must be HIGH when BUSY goes HIGH.
X
0
New convert commands ignored. Conversion "n" in progress.
TABLE 15. 7805ALP CONTROL LINE FUNCTION FOR READ AND CONVERT
CS
R/C
BUSY
OPERATION
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