2009 Teridian Semiconductor Corporation Rev 1.3 MR0:" />
參數(shù)資料
型號(hào)： 78Q2120C09-64CGT/F
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/35頁(yè)
文件大?。?/td> 0K
描述： TXRX 10/100 BASE 3.3V 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 以太網(wǎng)
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： MII
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 散裝
78Q2120C
10/100BASE-TX
Transceiver
Page: 12 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
MR0: Control Register (continued)
BIT
SYMBOL TYPE DEFAULT DESCRIPTION
0.8
DUPLEX
R/W
(1)
Duplex Mode: This bit determines whether the device supports full-
duplex or half-duplex. A ‘1’ indicates full-duplex operation and a ‘0’
indicates half-duplex. This bit will default to ‘0’ upon reset and will
be writeable if the TECH[2:0] pins are all logic zero and auto-
negotiation is not enabled. If auto-negotiation is not enabled and
the TECH[2:0] pins are set to indicate that only full-duplex is
supported, this bit will be forced to ‘1’ and will not be writeable. If
auto-negotiation is not enabled and the TECH[2:0] pins are set to
indicate that only half-duplex is supported, this bit will be forced to
‘0’ and will not be writeable. When auto-negotiation is enabled, this
bit will not be writeable and will have no effect on the device. If the
TECH[2:0] pins are brought to zero from another value, this bit will
retain its original value until it is overwritten.
0.7
COLT
R/W
0
Collision Test: When this bit is set to ‘1’, the device will assert the
COL signal in response to the assertion of the TX_EN signal.
Collision test is disabled if the PCSBP pin is high. Collision test can
be activated regardless of the duplex mode of operation.
0.6:0
RSVD
R
0
Reserved
MR1: Status Register
Bits 1.15 through 1.11 reflect the ability of the 78Q2120C as configured by the TECH[2:0] pins. They do not
reflect any ability changes made via the MII Management interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and
0.8 (DUPLEX).
BIT
SYMBOL TYPE DEFAULT DESCRIPTION
1.15
100T4
R
0
100BASE-T4 Ability: Reads ‘0’ to indicate the 78Q2120C does not
support 100Base-T4 mode.
1.14
100X_F
R
(1)
100BASE-TX Full Duplex Ability:
0 : Not able
1 : Able
1.13
100X_H
R
(1)
100BASE-TX Half Duplex Ability:
0 : Not able
1 : Able
1.12
10T_F
R
(1)
10BASE-T Full Duplex Ability:
0 : Not able
1 : Able
1.11
10T_H
R
(1)
10BASE-T Half Duplex Ability:
0 : Not able
1 : Able
1.10
100T2_F
R
0
100BASE-T2 Full Duplex Ability:
Reads ‘0’ to indicate the
78Q2120C does not support 100Base-T2 full duplex mode.
相關(guān)PDF資料
PDF描述
VE-JWF-MW-F2 CONVERTER MOD DC/DC 72V 100W
VE-JWF-MW-F1 CONVERTER MOD DC/DC 72V 100W
VE-JWD-MW-F4 CONVERTER MOD DC/DC 85V 100W
MAX3845UCQ+D IC SW/CBL DRVR DVI/HDMI 100TQFP
VE-JWB-MW-F3 CONVERTER MOD DC/DC 95V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
78Q2120C09-64CGTR/F 功能描述:TXRX 10/100 BASE 3.3V 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件
78Q2120C09-CGTR/F 功能描述:以太網(wǎng) IC 10-100 Fast Ethernet Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
78Q2120C09-DB 功能描述:以太網(wǎng)開發(fā)工具 78Q2120C09 Demo Boa RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
78Q2120-CGT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver
78Q2123 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:10/100BASE-TX Transceiver
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*