78Q2120C
10/100BASE-TX
Transceiver
DATA SHEET
Page: 1 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
TXD[3:0]
4B/5B Encoder,
Scrambler,
Parallel/Serial
Parallel/Serial,
Manchester Encoder
Manchester Decoder,
Parallel/Serial
Serial/Parallel
Descrambler,
5B/4B Decoder
NRZ/NRZI
MLT3 Encoder
TX CLK GEN
Carrier Sense,
Collision Detect
CLK
Recovery
Clock Reference
100M
10M
25MHz
Pulse Shaper
and Filter
Auto
Negotiation
Adaptive EQ,
Baseline Wander Correct,
MLT3 Decode, NRZI/NRZ
LEDs
LEDL
LEDBTX
LEDTX
LEDCOL
LEDBT
LEDFX
LEDRX
MDI
10M
100M
CKIN
PS
GND
VCC
MII
Registers
&
Interface
Logic
RXD[3:0]
TX_CLK
RX_CLK
4B/5B Encoder,
Scrambler,
Parallel/Serial
Parallel/Serial,
Manchester Encoder
Manchester Decoder,
Parallel/Serial
Serial/Parallel
Descrambler,
5B/4B Decoder
NRZ/NRZI
MLT3 Encoder
TX CLK GEN
Carrier Sense,
Collision Detect
CLK
Recovery
Clock Reference
100M
10M
25MHz
Pulse Shaper
and Filter
Auto
Negotiation
Adaptive EQ,
Baseline Wander Correct,
MLT3 Decode, NRZI/NRZ
LEDs
MDI
10M
100M
RXIP/N
TXOP/N
PS
GND
VCC
MII
Registers
&
Interface
Logic
January 2009
DESCRIPTION
The 78Q2120C is a 10BASE-T/100BASE-TX Fast
Ethernet transceiver. It includes integrated MII,
ENDECs, scrambler/descrambler, dual-speed clock
recovery, and full-featured auto-negotiation function.
The transmitter includes an on-chip pulse-shaper and
a low-power line driver. The receiver has an adaptive
equalizer and a baseline restoration circuit required
for accurate clock and data recovery. The transceiver
interfaces to Category-5 unshielded twisted pair (Cat-
5 UTP) cabling for 100BASE-TX/10BASE-T and
Category-3 unshielded twisted pair for 10BASE-T.
Connection to the line media is via 1:1 isolation
transformers. No external filter is required. Interface
to the MAC is accomplished through an IEEE-802.3
compliant Media Independent Interface (MII). The
product is fabricated in an advanced CMOS process
for high performance and low power operation.
FEATURES
10BASE-T/100BASE-TX IEEE-802.3 compliant
TX and RX functions requiring a dual 1:1
isolation transformer interface to the line
Integrated MII, 10BASE-T/100BASE-TX ENDEC,
100BASE-TX scrambler/descrambler, and full-
featured auto-negotiation function
Full duplex operation capable
PCS Bypass supports 5-bit symbol interface
Register-programmable transmit amplitude
Dual speed digital clock recovery
Automatic polarity correction during auto-
negotiation and 10BASE-T signal reception
Power-saving
and
power-down
modes
including transmitter disable
LED indicators: LINK, TX, RX, COL, 100, 10,
FDX
User programmable Interrupt pin
64-Pin TQFP (JEDEC LQFP) package
Single 3.3 V
± 0.3V Supply
BLOCK DIAGRAM