2009 Teridian Semiconductor Corporation Rev 1.3 MR16" />
參數(shù)資料
型號(hào)： 78Q2120C09-DB
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 78Q2120C
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
78Q2120C
10/100BASE-TX
Transceiver
Page: 16 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
MR16: Vendor Specific Register
BIT
SYMBOL TYPE DEFAULT DESCRIPTION
16.15
RPTR
R/W
(0)
Repeater Mode: When set, the 78Q2120C is put into Repeater mode
of operation. In this mode, full duplex is prohibited, CRS responds to
receive activity only and, in 10Base-T mode, the SQE test function is
disabled.
16.14
INPOL
R/W
0
When this bit is ‘0’, the INTR pin is forced low to signal an interrupt.
Setting this bit to ‘1’ causes the INTR pin to be forced high to signal
an interrupt.
16.13
RSVD
R
0
Reserved
16.12
TXHIM
R/W
0
Transmitter High-Impedance Mode:
When set, the TXOP/TXON
transmit pins and the TX_CLK pin are put into a high-impedance
state. The receive circuitry remains fully functional.
16.11
SQEI
R/W
0
SQE Test Inhibit: Setting this bit to ‘1’ disables 10Base-T SQE
testing. By default, this bit is ‘0’ and the SQE test is performed by
generating a COL pulse following the completion of a packet
transmission.
16.10
NL10
R/W
0
10Base-T Natural Loopback: Setting this bit to ‘1’ causes transmit
data received on the TXD0-3 pins to be automatically looped back to
the RXD[0:3] pins when 10Base-T mode is enabled.
16.9
RSVD
R/W
0
Reserved
16.8
RSVD
R/W
1
Reserved
16.7
RSVD
R/W
0
Reserved
16.6
RSVD
R/W
1
Reserved
16.5
APOL
R/W
0
Auto Polarity: During auto-negotiation and 10BASE-T mode, the
78Q2120C is able to automatically invert the received signal due to a
wrong polarity connection. It does so by detecting the polarity of the
link pulses. Setting this bit to ‘1’ disables this feature.
16.4
RVSPOL
R/W
0
Reverse Polarity: The reverse polarity is detected either through 8
inverted 10Base-T link pulses (NLP) or through one burst of inverted
clock pulses in the auto-negotiation link pulses (FLP). When the
reverse polarity is detected and if the Auto Polarity feature is
enabled, the 78Q2120C will invert the receive data input and set this
bit to ‘1’. If Auto Polarity is disabled, then this bit is writeable. Writing
a ‘1’ to this bit forces the polarity of the receive signal to be reversed.
16.3:2
RSVD
R/W
0h
Reserved: Must set to ‘00’.
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